Commit Graph

39 Commits

Author SHA1 Message Date
bjorn3
bb8fa40ef0 Rustfmt 2019-10-02 11:50:44 -07:00
bjorn3
c274d81b5b Fix it 2019-10-02 11:50:44 -07:00
bjorn3
10e226f9ff Always use extern crate std in cranelift-codegen 2019-10-02 11:50:44 -07:00
Andrew Brown
ba393afd4d Add x86 legalization for SIMD ineg 2019-09-30 13:54:30 -07:00
Benjamin Bouvier
c3d01756a3 Baldrdash: uses ECX for the WasmTableCallSigReg on x86 32-bits; 2019-09-30 15:11:06 +02:00
Ujjwal Sharma
43a891dfa2 [codegen] add intcc conditions for reading overflow flag
Add conditions to IntCC for checking the overflow flag (Overflow,
NotOverflow).
2019-09-25 11:42:58 +02:00
Ujjwal Sharma
6e131e5347 [codegen] add intcc conditions for reading carry flag
Add conditions to IntCC for checking the carry flag (Carry, NotCarry).

Fixes: https://github.com/CraneStation/cranelift/issues/980
2019-09-24 15:12:09 -07:00
Andrew Brown
af1499ce99 Add x86 implementation of shuffle 2019-09-19 10:53:40 -07:00
bjorn3
add6a4f269 Correctly zero extend operand of fcvt_from_uint for 8ints and 16bit ints (#997)
Fixes #996
2019-09-18 10:06:15 +02:00
Andrew Brown
295b2ef614 Avoid extra register movement when lowering an x86 insertlane to a float vector 2019-09-10 10:45:12 -07:00
Andrew Brown
00bedca274 Avoid extra register movement when lowering the x86 extractlane of a float vector
This commit is based on the assumption that floats are already stored in XMM registers in x86. When extracting a lane, cranelift was moving the float to a regular register and back to an XMM register; this change avoids this by shuffling the float value to the lowest bits of the XMM register. It also assumes that the upper bits can be left as is (instead of zeroing them out).
2019-09-10 10:45:12 -07:00
Nicolas B. Pierron
90b0b86f5c Simplify isa_builder macro 2019-09-09 13:30:02 +02:00
Benjamin Bouvier
e35cf861db Fixes #984: Add a isa::lookup_by_name function;
This removes the explicit dependency on target-lexicon for the embedder,
which can instead use the ISA's name directly. It can simplify
dependency management, in particular avoid the need for synchronizing
the target-lexicon dependencies versions.

It also tweak the error when an ISA isn't built as part of Cranelift to
be a SupportDisabled error; this was dead code before this.
2019-09-06 16:19:01 +02:00
Benjamin Bouvier
660b8b28b8 [codegen] Add a pinned register that's entirely under the control of the user; 2019-09-06 16:18:27 +02:00
Pat Hickey
89d741f8ae upgrade to target-lexicon 0.8.0
* the target-lexicon crate no longer has or needs the std feature
  in cargo, so we can delete all default-features=false, any mentions
  of its std feature, and the nostd configs in many lib.rs files
* the representation of arm architectures has changed, so some case
  statements needed refactoring
2019-09-04 15:12:17 -07:00
Benjamin Bouvier
44942a26a2 Tweak comments; 2019-09-03 14:08:37 +02:00
Andrew Brown
684721ca29 Add x86 recipe for vconst 2019-08-26 16:12:06 -07:00
Carmen Kwan
19257f80c1 Add reference types R32 and R64
-Add resumable_trap, safepoint, isnull, and null instructions
-Add Stackmap struct and StackmapSink trait

Co-authored-by: Mir Ahmed <mirahmed753@gmail.com>
Co-authored-by: Dan Gohman <sunfish@mozilla.com>
2019-08-16 11:35:16 -07:00
Benjamin Bouvier
2ee35b7ea1 Implement a Windows Baldrdash calling convention; 2019-08-16 14:25:15 +02:00
Benjamin Bouvier
d8d3602257 Adds the libcall_call_conv setting and use it for libcall calls expansion; 2019-08-12 16:12:00 -07:00
Andrew Brown
c39a9b4e3f Assign vector arguments to FPR registers 2019-07-16 17:07:44 -07:00
Andrew Brown
f2c48009e8 Disable SIMD features by default 2019-07-16 17:07:44 -07:00
Nicolas B. Pierron
8edc40cb49 BB-like manual legalization for x86 ISA 2019-07-12 14:20:26 +02:00
Benjamin Bouvier
f11fc34066 Build fix: add crates::predicates to the Riscv enc_tables file; 2019-07-09 11:31:21 +02:00
Benjamin Bouvier
cd4c28ad97 [meta] Legalization: Unprefix some module paths to make code neater; 2019-07-09 10:56:50 +02:00
Benjamin Bouvier
563525b090 [meta] Remove mentions to Python in comments of the non-meta crate; 2019-07-05 17:50:17 +02:00
Benjamin Bouvier
88307f693a [meta] Generate the encodings files; 2019-07-05 17:50:17 +02:00
Benjamin Bouvier
d7d48d5cc6 Add the dyn keyword before trait objects; 2019-06-24 11:42:26 +02:00
Lars T Hansen
420850adf0 Record information about sections of emitted code+data.
The result of the emitter is a vector of bytes holding machine code,
jump tables, and (in the future) other read-only data.  Some clients,
notably Firefox's Wasm compiler, needs to separate the machine code
from the data in order to insert more code directly after the code
generated by Cranelift.

To make such separation possible, we record more information about the
emitted bytes: the sizes of each of the sections of code, jump tables,
and read-only data, as well as the locations within the code that
reference (PC-relatively) the jump tables and read-only data.
2019-05-31 08:39:57 +02:00
Lars T Hansen
5cd0724fef Clarify that FixedTied constraints are not Tied (#756)
* Clarify that FixedTied constraints are not Tied
2019-05-02 14:33:54 +02:00
Benjamin Bouvier
18a5386c08 Remove and reorganize IntCC/FloatCC imports to avoid a build warning; 2019-05-02 10:08:53 +02:00
Benjamin Bouvier
95e6fc9efc Avoid inserting checks during div/rem legalization when the input is a constant immediate; 2019-04-25 16:58:41 +02:00
carolinecullen
0166d6507a Adding comment about copying RiscV abi file into ARM32. 2019-04-08 17:06:08 -07:00
carolinecullen
8ab7170a07 Updated comments. 2019-04-08 17:06:08 -07:00
carolinecullen
72bc035d70 Beginnings of arm32 backend. 2019-04-08 17:06:08 -07:00
Steffen Butzer
92b3987e54 windows/x64 call convention: only use XMM0 for float return values (#691) 2019-03-11 11:44:44 +01:00
Steffen Butzer
2a519092a0 Use single index for param register allocation for windows callconv (… (#693)
* Use single index for param register allocation for windows callconv (#691)

The used registers depend entirely on the parameter index (1st, 2nd, 3rd, 4th, ... param)
and we cannot shift unused registers to other indexes, if they are not designated for
the use for that parameter index.
2019-03-05 12:17:41 +01:00
Benjamin Bouvier
a45b814de8 Fixes #13: Enable conditional compilation of ISAs through features; 2019-02-12 08:19:57 -08:00
lazypassion
747ad3c4c5 moved crates in lib/ to src/, renamed crates, modified some files' text (#660)
moved crates in lib/ to src/, renamed crates, modified some files' text (#660)
2019-01-28 15:56:54 -08:00