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136 Commits

Author SHA1 Message Date
Andrew Brown
6605f308b3 Fix static analysis warnings 2019-08-20 10:21:12 -07:00
Andrew Brown
d492cf7e0e Avoid unnecessary lane calculations in codegen code 
This refactor moves the calculation of the number of lanes to code closer to where the Instruction/BoundInstruction is bound.
 2019-08-20 10:21:12 -07:00
Andrew Brown
3fdc78174f Add x86 implementation of extractlane instruction 2019-08-20 10:21:12 -07:00
Carmen Kwan
19257f80c1 Add reference types R32 and R64 
-Add resumable_trap, safepoint, isnull, and null instructions
-Add Stackmap struct and StackmapSink trait

Co-authored-by: Mir Ahmed <mirahmed753@gmail.com>
Co-authored-by: Dan Gohman <sunfish@mozilla.com>
 2019-08-16 11:35:16 -07:00
David Lattimore
383ce584ae Fix an assertion that wasn't doing what it said 2019-08-05 15:22:10 +02:00
Benjamin Bouvier
627ba24b59 Simplify jump table instructions and add missing conversion; 
This makes non-legalized jump table instructions operate on operands with
pointer-sized types. This means we need to extend smaller types into the
pointer-sized operand, when the two don't match.
 2019-08-02 18:39:39 +02:00
Andrew Brown
084e279def Add x86 implementation of splat instruction 2019-07-16 17:07:44 -07:00
Andrew Brown
3b36a1d1d8 Add x86 implementation of insertlane instruction 2019-07-16 17:07:44 -07:00
Andrew Brown
683e7c75a3 Add x86-specific shuffle instructions 
This includes both PSHUFD and PSHUFB; these are necessary to legalize future SIMD instructions.
 2019-07-16 17:07:44 -07:00
Andrew Brown
61772e9775 Add raw_bitcast instruction 
Casts bits as a different type of the same width with no change to the data (unlike bitcast)
 2019-07-16 17:07:44 -07:00
Andrew Brown
5f0e5567c1 Add scalar_to_vector instruction 
Moves scalar values in a GPR register to an FPR register
 2019-07-16 17:07:44 -07:00
Andrew Brown
659725b465 Add x86-specific SIMD settings, e.g. SSE2 
Also, ties SIMD ISA predicates to the shared enable_simd setting
 2019-07-16 17:07:44 -07:00
Benjamin Bouvier
062ed8f6ea [docs] Remove rst annotations in instructions doc comments; 2019-07-11 11:48:45 +02:00
Benjamin Bouvier
84a6795873 [meta] Riscv: add back stacknull encodings for copy_nop; 2019-07-10 17:51:09 +02:00
Benjamin Bouvier
fd03677292 [meta] Recipes and encodings descriptions for x86; 2019-07-05 11:38:51 +02:00
Benjamin Bouvier
ca277422bb [meta] Recipes and encodings descriptions for RiscV; 2019-07-05 11:38:51 +02:00
Benjamin Bouvier
21aaf0c89f [meta] Add cdsl facilities for encodings and recipes; 
Co-authored-by: Benjamin Bouvier <public@benj.me>
Co-authored-by: bjorn3 <bjorn3@users.noreply.github.com>
 2019-07-05 11:38:51 +02:00
Benjamin Bouvier
e34a4759cd [meta] Fix typo in x86 setting name use_lzcnt; 2019-07-03 18:39:28 +02:00
Benjamin Bouvier
f1d1d1e960 [meta] Uniquely number every instruction in the Rust crate; 2019-07-03 18:39:28 +02:00
Benjamin Bouvier
70f79d23bf [meta] Make Builders build() instead of finish(); 2019-05-29 14:05:01 +02:00
Benjamin Bouvier
d9277f249b [meta] Introduce the InstructionGroupBuilder; 
This follows the rest of the code base data structures, where we have a
mutable data structure builder; once the data structure is constructed,
it's immutable.

This also makes the definition of instructions easier, and it paves the
way for defining immediate variants.
 2019-05-29 14:05:01 +02:00
Benjamin Bouvier
22a6823496 [meta] Rename cdsl/inst to cdsl/instructions; 2019-05-29 14:05:01 +02:00
Benjamin Bouvier
6935033c9e [meta] Have bind() be a method of {Bound,}Instruction instead of a static method; 2019-05-23 14:31:00 +02:00
Benjamin Bouvier
a46b2d7173 [meta] Move ApplyTarget/bind to cdsl/inst; 2019-05-23 14:31:00 +02:00
Benjamin Bouvier
cbbb7a220e [meta] Move x86 registers generation to their own file; 2019-05-22 10:55:02 +02:00
Benjamin Bouvier
92109f664c [meta] Move x86 settings generation to their own file; 2019-05-22 10:55:02 +02:00
Benjamin Bouvier
f335c5c56c [meta] Small fixes in the settings generation; 2019-05-03 12:01:12 +02:00
Benjamin Bouvier
390cfb37da [meta] Use named predicates for x86 settings in the Rust crate too; 
And generate them using the same deterministic order that the Python
code uses.
 2019-05-03 12:01:12 +02:00
Benjamin Bouvier
1f21349c4b [meta] Add CPU modes to the meta crate; 2019-04-25 11:44:56 +02:00
Benjamin Bouvier
d00e42ede3 [meta] Port shared and x86 legalizations to the Rust crate; 2019-04-25 11:44:56 +02:00
Benjamin Bouvier
6053201128 [meta] Move the TypeSet building out of the TypeVar builder so as to test it; 2019-04-02 17:30:50 +02:00
Benjamin Bouvier
3c31eac48c [meta] Port Instruction/InstructionGroup to the Rust meta crate; 2019-03-28 14:13:29 +01:00
Benjamin Bouvier
a45b814de8 Fixes #13: Enable conditional compilation of ISAs through features; 2019-02-12 08:19:57 -08:00
Benjamin Bouvier
049f067168 [meta] Build registers with their own builder and immutably construct the TargetIsa; 2019-02-12 08:19:57 -08:00
Benjamin Bouvier
25fdda6134 [meta] Move source generation responsibility into the meta crate itself; 2019-02-12 08:19:57 -08:00
lazypassion
747ad3c4c5 moved crates in lib/ to src/, renamed crates, modified some files' text (#660) 
moved crates in lib/ to src/, renamed crates, modified some files' text (#660)
 2019-01-28 15:56:54 -08:00