Commit Graph

627 Commits

Author SHA1 Message Date
Andrew Brown
636ef98024 Use existing is_equal predicate with the newly-shared condition codes
This removes the `HasConditionCode(&'static str)` predicate and the associated issues with that.
2019-09-24 09:33:07 -07:00
Andrew Brown
c648fa3d06 Move condcodes.rs to a new crate, cranelift-codegen-shared
This move allows the `IntCC`/`FloatCC` enums to be used in both meta (for predicate matching) and in codegen. To avoid breaking any code dependent on the previous location of condcodes.rs (`cranelift-codegen/src/condcodes.rs`), the module is re-exported under `cranelift_codegen::ir`.
2019-09-24 09:33:07 -07:00
Andrew Brown
a3db30d97e Add x86 encoding for SIMD icmp eq
Also adds a predicate for matching the `eq` IntCC code (TODO this should be replaced by something more general)
2019-09-24 09:33:07 -07:00
Andrew Brown
702155b19b Optimize vconst for x86 when immediate contains all zeroes or ones
Instead of using MOVUPS to expensively load bits from memory, this change uses a predicate to optimize vconst without a memory access:
 - when the 128-bit immediate is all zeroes in all bits, use PXOR to zero out an XMM register
 - when the 128-bit immediate is all ones in all bits, use PCMPEQB to set an XMM register to all ones

This leaves the constant data in the constant pool, which may increase code size (TODO)
2019-09-24 09:33:07 -07:00
Nicolas B. Pierron
694de912a5 Update brnz.i128 legalization to use non-extended basic blocks. 2019-09-24 15:55:58 +02:00
Nicolas B. Pierron
26cfbafb32 Add ebb macro to insert a new blocks in legalization output. 2019-09-24 15:55:58 +02:00
Nicolas B. Pierron
0c1f17d6dd Add empty_vararg literal to generate jump instruction. 2019-09-24 15:55:58 +02:00
Nicolas B. Pierron
614fb7b526 Factor out the var_index function. 2019-09-24 15:55:58 +02:00
Benjamin Bouvier
f0244516c5 [meta] Make more things pub(crate) instead of pub;
This could help the compiler find unused fields/methods. It didn't find any
during this migration.
2019-09-23 14:42:20 +02:00
Benjamin Bouvier
c2587c9d61 [meta] Remove Literal's kind field; 2019-09-23 14:42:20 +02:00
Anthony Ramine
178241625c Use slice::from_ref and slice::from_mut 2019-09-23 10:36:03 +02:00
Dan Gohman
411545ed9a Bump version to 0.43.1 2019-09-20 14:11:15 -07:00
Andrew Brown
2330ca7e2c Fix incorrect regmove and fill encodings for SIMD types
- `fill` attempted to use a GPR recipe, `fillSib32`, instead of its FPR equivalent, `ffillSib32` (code compiled without error but incorrect instructions were allowed, e.g. `v1 = regmove v0, %rdi -> %xmm0`
- `regmove` could be encoded with a GPR recipe, `rmov`, which hid the above incorrectness; now only FPR-to-FPR regmoves are allowed using the `frmov` recipe
2019-09-20 14:02:03 -07:00
Nick Fitzgerald
9b8e7b511e tidy: Remove extra semicolons
These were causing compilation warnings.
2019-09-19 16:25:49 -07:00
Dan Gohman
5c5eabb8d0 Bump version to 0.43.0 2019-09-19 12:23:51 -07:00
Andrew Brown
fe25abeb0d Add x86 encodings for vector copy, copy_nop, fill_nop 2019-09-19 12:04:14 -07:00
Andrew Brown
766cf8ddfd Add x86 implemention for SIMD iadd 2019-09-19 12:04:14 -07:00
Andrew Brown
7e6913e362 Add x86 encodings for vector store, load, fill, spill, and regmove 2019-09-19 12:04:14 -07:00
Andrew Brown
e72434e58f Add boolean encodings for x86
Includes and, or, xor, not, and regmove; TODO re-factor PerCpuModeEncodings to avoid code duplication
2019-09-19 10:53:40 -07:00
Andrew Brown
af1499ce99 Add x86 implementation of shuffle 2019-09-19 10:53:40 -07:00
julian-seward1
9e088e4164 Reorganise optimisation level settings, and make the insn shrink pass optional (#1044)
This patch:

* removes the "default" opt level, on the basis that it has no definition and
  is referred to nowhere in the compiler.

* renames the "fastest" level to "none".  The resulting set of transformations
  is unchanged.

* renames the "best" level to "speed_and_size".  The resulting set of
  transformations is unchanged.

* adds a new level, "speed".  This is the same as "speed_and_size" except that
  it omits transformations aimed only at reducing code size.  Currently it
  omits only the insn shrinking pass.
2019-09-19 18:51:25 +02:00
bjorn3
add6a4f269 Correctly zero extend operand of fcvt_from_uint for 8ints and 16bit ints (#997)
Fixes #996
2019-09-18 10:06:15 +02:00
Andy Wortman
99380fad1a Use 'xor r, r' to set registers to 0 instead of mov (#766) 2019-09-16 16:35:55 +02:00
Ujjwal Sharma
3418fb6e18 [codegen] reintroduce support for carry and borrow instructions in RI… (#1005)
Reintroduce support for iadd carry variants and isub borrow variants for
RISC ISAs which had been removed in
https://github.com/CraneStation/cranelift/pull/961 and
https://github.com/CraneStation/cranelift/pull/962 because of the lack
of a proper flags register in RISC architectures.
2019-09-13 17:27:49 +02:00
Benjamin Bouvier
3aa76b558c Legalize i64.const by breaking it into two i32.const, on 32-bits platforms; 2019-09-10 19:50:34 +02:00
Andrew Brown
6f1ed94e82 Fix documentation 2019-09-10 10:45:12 -07:00
Andrew Brown
295b2ef614 Avoid extra register movement when lowering an x86 insertlane to a float vector 2019-09-10 10:45:12 -07:00
Andrew Brown
3dfc68afb1 Avoid extra register movement when lowering the x86 scalar_to_vector of a float value 2019-09-10 10:45:12 -07:00
Andrew Brown
00bedca274 Avoid extra register movement when lowering the x86 extractlane of a float vector
This commit is based on the assumption that floats are already stored in XMM registers in x86. When extracting a lane, cranelift was moving the float to a regular register and back to an XMM register; this change avoids this by shuffling the float value to the lowest bits of the XMM register. It also assumes that the upper bits can be left as is (instead of zeroing them out).
2019-09-10 10:45:12 -07:00
Andrew Brown
ebc783e49b Use raw_bitcast when legalizing splat
raw_bitcast matches the intent of this legalization more clearly (to simply change the CLIF type without changing any bits) and the additional null encodings added are necessary for later instructions
2019-09-10 10:45:12 -07:00
Ujjwal Sharma
345b2dc0cc [codegen] add new recipe "rout" (#1014)
* [codegen] add new recipe "rout"

Add a new recipe "rout" intended to be used by arithematic operations
that output flags, currently being used for `iadd_cout` and `isub_bout`.

Fixes: https://github.com/CraneStation/cranelift/issues/1009
2019-09-10 12:55:24 +02:00
bjorn3
0273eb84e0 Fix rebase 2019-09-07 09:55:09 -07:00
bjorn3
e8d4ef7c3d Fix review comments 2019-09-07 09:55:09 -07:00
bjorn3
e2b2b520eb Fix compilation 2019-09-07 09:55:09 -07:00
bjorn3
ffa1e946a7 Fix compilation 2019-09-07 09:55:09 -07:00
bjorn3
67593d997b Add b128 type to fix tests 2019-09-07 09:55:09 -07:00
bjorn3
fa9602df80 Legalize load.i128 and store.i128 2019-09-07 09:55:09 -07:00
bjorn3
0d5b87038a Rustfmt 2019-09-07 09:55:09 -07:00
bjorn3
599b48d95f Narrowing legalize some more bitops 2019-09-07 09:55:09 -07:00
bjorn3
762b5e494b Legalize brz.i128 and brnz.i128 2019-09-07 09:55:09 -07:00
bjorn3
83ac6dd4d4 [meta] Add some Debug derives 2019-09-07 09:55:09 -07:00
bjorn3
a43a3a5e9f [meta] Give a nicer error message when a legalization uses an incorrect number of arguments 2019-09-07 09:55:09 -07:00
bjorn3
8d0e8f8931 [meta] Fix legalization in presence of varargs 2019-09-07 09:55:09 -07:00
bjorn3
c9a25abbc4 Basic i128 support 2019-09-07 09:55:09 -07:00
Benjamin Bouvier
c1609b70e8 [codegen] Allow using the pinned register as the heap base via a setting; 2019-09-06 16:18:27 +02:00
Benjamin Bouvier
660b8b28b8 [codegen] Add a pinned register that's entirely under the control of the user; 2019-09-06 16:18:27 +02:00
Benjamin Bouvier
d1d2e790b9 [meta] Morph a few pub into pub(crate), and remove dead code; 2019-09-06 15:47:20 +02:00
Benjamin Bouvier
8fba449b7b [meta] Introduce the EntityRefs structure instead of using dynamic lookup; 2019-09-06 15:47:20 +02:00
Benjamin Bouvier
29e3ec51c1 [meta] Introduce the Immediates structure instead of using dynamic lookup; 2019-09-06 15:47:20 +02:00
Dan Gohman
d858ebb4aa Bump version to 0.42.0 2019-09-05 17:36:04 -07:00