From ffe89cdc0a55fbd5611093d34f1633890b4f21f7 Mon Sep 17 00:00:00 2001 From: Dan Gohman Date: Mon, 26 Mar 2018 21:34:15 -0700 Subject: [PATCH] Rename %eflags to %rflags. EFLAGS is a subregister of RFLAGS. For consistency with GPRs where we use the 64-bit names to refer to the registers, use the 64-bit name for RFLAGS as well. --- .../baseline_clz_ctz_popcount_encoding.cton | 24 ++++++------- .../filetests/isa/intel/binary32-float.cton | 14 ++++---- cranelift/filetests/isa/intel/binary32.cton | 16 ++++----- .../filetests/isa/intel/binary64-float.cton | 14 ++++---- cranelift/filetests/isa/intel/binary64.cton | 28 +++++++-------- lib/cretonne/meta/isa/intel/recipes.py | 36 +++++++++---------- lib/cretonne/meta/isa/intel/registers.py | 2 +- lib/cretonne/src/isa/intel/binemit.rs | 2 +- 8 files changed, 68 insertions(+), 68 deletions(-) diff --git a/cranelift/filetests/isa/intel/baseline_clz_ctz_popcount_encoding.cton b/cranelift/filetests/isa/intel/baseline_clz_ctz_popcount_encoding.cton index 0b7003449d..2e552b7145 100644 --- a/cranelift/filetests/isa/intel/baseline_clz_ctz_popcount_encoding.cton +++ b/cranelift/filetests/isa/intel/baseline_clz_ctz_popcount_encoding.cton @@ -15,56 +15,56 @@ ebb0: [-,%r11] v10 = iconst.i64 0x1234 ; asm: bsfq %r11, %rcx - [-,%rcx,%eflags] v11, v12 = x86_bsf v10 ; bin: 49 0f bc cb + [-,%rcx,%rflags] v11, v12 = x86_bsf v10 ; bin: 49 0f bc cb [-,%rdx] v14 = iconst.i64 0x5678 ; asm: bsfq %rdx, %r12 - [-,%r12,%eflags] v15, v16 = x86_bsf v14 ; bin: 4c 0f bc e2 + [-,%r12,%rflags] v15, v16 = x86_bsf v14 ; bin: 4c 0f bc e2 ; asm: bsfq %rdx, %rdi - [-,%rdi,%eflags] v17, v18 = x86_bsf v14 ; bin: 48 0f bc fa + [-,%rdi,%rflags] v17, v18 = x86_bsf v14 ; bin: 48 0f bc fa ; 32-bit wide bsf [-,%r11] v20 = iconst.i32 0x1234 ; asm: bsfl %r11d, %ecx - [-,%rcx,%eflags] v21, v22 = x86_bsf v20 ; bin: 41 0f bc cb + [-,%rcx,%rflags] v21, v22 = x86_bsf v20 ; bin: 41 0f bc cb [-,%rdx] v24 = iconst.i32 0x5678 ; asm: bsfl %edx, %r12d - [-,%r12,%eflags] v25, v26 = x86_bsf v24 ; bin: 44 0f bc e2 + [-,%r12,%rflags] v25, v26 = x86_bsf v24 ; bin: 44 0f bc e2 ; asm: bsfl %edx, %esi - [-,%rsi,%eflags] v27, v28 = x86_bsf v24 ; bin: 0f bc f2 + [-,%rsi,%rflags] v27, v28 = x86_bsf v24 ; bin: 0f bc f2 ; 64-bit wide bsr [-,%r11] v30 = iconst.i64 0x1234 ; asm: bsrq %r11, %rcx - [-,%rcx,%eflags] v31, v32 = x86_bsr v30 ; bin: 49 0f bd cb + [-,%rcx,%rflags] v31, v32 = x86_bsr v30 ; bin: 49 0f bd cb [-,%rdx] v34 = iconst.i64 0x5678 ; asm: bsrq %rdx, %r12 - [-,%r12,%eflags] v35, v36 = x86_bsr v34 ; bin: 4c 0f bd e2 + [-,%r12,%rflags] v35, v36 = x86_bsr v34 ; bin: 4c 0f bd e2 ; asm: bsrq %rdx, %rdi - [-,%rdi,%eflags] v37, v38 = x86_bsr v34 ; bin: 48 0f bd fa + [-,%rdi,%rflags] v37, v38 = x86_bsr v34 ; bin: 48 0f bd fa ; 32-bit wide bsr [-,%r11] v40 = iconst.i32 0x1234 ; asm: bsrl %r11d, %ecx - [-,%rcx,%eflags] v41, v42 = x86_bsr v40 ; bin: 41 0f bd cb + [-,%rcx,%rflags] v41, v42 = x86_bsr v40 ; bin: 41 0f bd cb [-,%rdx] v44 = iconst.i32 0x5678 ; asm: bsrl %edx, %r12d - [-,%r12,%eflags] v45, v46 = x86_bsr v44 ; bin: 44 0f bd e2 + [-,%r12,%rflags] v45, v46 = x86_bsr v44 ; bin: 44 0f bd e2 ; asm: bsrl %edx, %esi - [-,%rsi,%eflags] v47, v48 = x86_bsr v44 ; bin: 0f bd f2 + [-,%rsi,%rflags] v47, v48 = x86_bsr v44 ; bin: 0f bd f2 ; 64-bit wide cmov diff --git a/cranelift/filetests/isa/intel/binary32-float.cton b/cranelift/filetests/isa/intel/binary32-float.cton index 8f60cf20be..94db28d26e 100644 --- a/cranelift/filetests/isa/intel/binary32-float.cton +++ b/cranelift/filetests/isa/intel/binary32-float.cton @@ -221,11 +221,11 @@ ebb0: [-,%rdx] v307 = fcmp ule v11, v10 ; bin: 0f 2e d5 0f 96 c2 ; asm: ucomiss %xmm2, %xmm5 - [-,%eflags] v310 = ffcmp v10, v11 ; bin: 0f 2e ea + [-,%rflags] v310 = ffcmp v10, v11 ; bin: 0f 2e ea ; asm: ucomiss %xmm2, %xmm5 - [-,%eflags] v311 = ffcmp v11, v10 ; bin: 0f 2e d5 + [-,%rflags] v311 = ffcmp v11, v10 ; bin: 0f 2e d5 ; asm: ucomiss %xmm5, %xmm5 - [-,%eflags] v312 = ffcmp v10, v10 ; bin: 0f 2e ed + [-,%rflags] v312 = ffcmp v10, v10 ; bin: 0f 2e ed return } @@ -436,11 +436,11 @@ ebb0: [-,%rdx] v307 = fcmp ule v11, v10 ; bin: 66 0f 2e d5 0f 96 c2 ; asm: ucomisd %xmm2, %xmm5 - [-,%eflags] v310 = ffcmp v10, v11 ; bin: 66 0f 2e ea + [-,%rflags] v310 = ffcmp v10, v11 ; bin: 66 0f 2e ea ; asm: ucomisd %xmm2, %xmm5 - [-,%eflags] v311 = ffcmp v11, v10 ; bin: 66 0f 2e d5 + [-,%rflags] v311 = ffcmp v11, v10 ; bin: 66 0f 2e d5 ; asm: ucomisd %xmm5, %xmm5 - [-,%eflags] v312 = ffcmp v10, v10 ; bin: 66 0f 2e ed + [-,%rflags] v312 = ffcmp v10, v10 ; bin: 66 0f 2e ed return } @@ -448,7 +448,7 @@ ebb0: function %cpuflags_float(f32 [%xmm0]) { ebb0(v0: f32 [%xmm0]): ; asm: ucomiss %xmm0, %xmm0 - [-,%eflags] v1 = ffcmp v0, v0 ; bin: 0f 2e c0 + [-,%rflags] v1 = ffcmp v0, v0 ; bin: 0f 2e c0 jump ebb1 diff --git a/cranelift/filetests/isa/intel/binary32.cton b/cranelift/filetests/isa/intel/binary32.cton index 56301607cc..771bb19af2 100644 --- a/cranelift/filetests/isa/intel/binary32.cton +++ b/cranelift/filetests/isa/intel/binary32.cton @@ -473,9 +473,9 @@ ebb0: ebb1: ; asm: cmpl %esi, %ecx - [-,%eflags] v10 = ifcmp v1, v2 ; bin: 39 f1 + [-,%rflags] v10 = ifcmp v1, v2 ; bin: 39 f1 ; asm: cmpl %ecx, %esi - [-,%eflags] v11 = ifcmp v2, v1 ; bin: 39 ce + [-,%rflags] v11 = ifcmp v2, v1 ; bin: 39 ce ; asm: je ebb1 brif eq v11, ebb1 ; bin: 74 fa @@ -543,19 +543,19 @@ ebb1: ; Stack check. ; asm: cmpl %esp, %ecx - [-,%eflags] v40 = ifcmp_sp v1 ; bin: 39 e1 + [-,%rflags] v40 = ifcmp_sp v1 ; bin: 39 e1 ; asm: cmpl %esp, %esi - [-,%eflags] v41 = ifcmp_sp v2 ; bin: 39 e6 + [-,%rflags] v41 = ifcmp_sp v2 ; bin: 39 e6 ; asm: cmpl $-100, %ecx - [-,%eflags] v42 = ifcmp_imm v1, -100 ; bin: 83 f9 9c + [-,%rflags] v42 = ifcmp_imm v1, -100 ; bin: 83 f9 9c ; asm: cmpl $100, %esi - [-,%eflags] v43 = ifcmp_imm v2, 100 ; bin: 83 fe 64 + [-,%rflags] v43 = ifcmp_imm v2, 100 ; bin: 83 fe 64 ; asm: cmpl $-10000, %ecx - [-,%eflags] v44 = ifcmp_imm v1, -10000 ; bin: 81 f9 ffffd8f0 + [-,%rflags] v44 = ifcmp_imm v1, -10000 ; bin: 81 f9 ffffd8f0 ; asm: cmpl $10000, %esi - [-,%eflags] v45 = ifcmp_imm v2, 10000 ; bin: 81 fe 00002710 + [-,%rflags] v45 = ifcmp_imm v2, 10000 ; bin: 81 fe 00002710 return } diff --git a/cranelift/filetests/isa/intel/binary64-float.cton b/cranelift/filetests/isa/intel/binary64-float.cton index 69bfeb6c36..b362b7eb4a 100644 --- a/cranelift/filetests/isa/intel/binary64-float.cton +++ b/cranelift/filetests/isa/intel/binary64-float.cton @@ -235,11 +235,11 @@ ebb0: [-,%rdx] v307 = fcmp ule v11, v10 ; bin: 44 0f 2e d5 0f 96 c2 ; asm: ucomiss %xmm10, %xmm5 - [-,%eflags] v310 = ffcmp v10, v11 ; bin: 41 0f 2e ea + [-,%rflags] v310 = ffcmp v10, v11 ; bin: 41 0f 2e ea ; asm: ucomiss %xmm10, %xmm5 - [-,%eflags] v311 = ffcmp v11, v10 ; bin: 44 0f 2e d5 + [-,%rflags] v311 = ffcmp v11, v10 ; bin: 44 0f 2e d5 ; asm: ucomiss %xmm5, %xmm5 - [-,%eflags] v312 = ffcmp v10, v10 ; bin: 0f 2e ed + [-,%rflags] v312 = ffcmp v10, v10 ; bin: 0f 2e ed return } @@ -470,11 +470,11 @@ ebb0: [-,%rdx] v307 = fcmp ule v11, v10 ; bin: 66 44 0f 2e d5 0f 96 c2 ; asm: ucomisd %xmm10, %xmm5 - [-,%eflags] v310 = ffcmp v10, v11 ; bin: 66 41 0f 2e ea + [-,%rflags] v310 = ffcmp v10, v11 ; bin: 66 41 0f 2e ea ; asm: ucomisd %xmm10, %xmm5 - [-,%eflags] v311 = ffcmp v11, v10 ; bin: 66 44 0f 2e d5 + [-,%rflags] v311 = ffcmp v11, v10 ; bin: 66 44 0f 2e d5 ; asm: ucomisd %xmm5, %xmm5 - [-,%eflags] v312 = ffcmp v10, v10 ; bin: 66 0f 2e ed + [-,%rflags] v312 = ffcmp v10, v10 ; bin: 66 0f 2e ed return } @@ -482,7 +482,7 @@ ebb0: function %cpuflags_float(f32 [%xmm0]) { ebb0(v0: f32 [%xmm0]): ; asm: ucomiss %xmm0, %xmm0 - [-,%eflags] v1 = ffcmp v0, v0 ; bin: 0f 2e c0 + [-,%rflags] v1 = ffcmp v0, v0 ; bin: 0f 2e c0 jump ebb1 diff --git a/cranelift/filetests/isa/intel/binary64.cton b/cranelift/filetests/isa/intel/binary64.cton index 5741f18041..3c35bd2a0c 100644 --- a/cranelift/filetests/isa/intel/binary64.cton +++ b/cranelift/filetests/isa/intel/binary64.cton @@ -584,9 +584,9 @@ ebb0: ebb1: ; asm: cmpq %r10, %rcx - [-,%eflags] v10 = ifcmp v1, v2 ; bin: 4c 39 d1 + [-,%rflags] v10 = ifcmp v1, v2 ; bin: 4c 39 d1 ; asm: cmpq %rcx, %r10 - [-,%eflags] v11 = ifcmp v2, v1 ; bin: 49 39 ca + [-,%rflags] v11 = ifcmp v2, v1 ; bin: 49 39 ca ; asm: je ebb1 brif eq v11, ebb1 ; bin: 74 f8 @@ -654,19 +654,19 @@ ebb1: ; Stack check. ; asm: cmpq %rsp, %rcx - [-,%eflags] v40 = ifcmp_sp v1 ; bin: 48 39 e1 + [-,%rflags] v40 = ifcmp_sp v1 ; bin: 48 39 e1 ; asm: cmpq %rsp, %r10 - [-,%eflags] v41 = ifcmp_sp v2 ; bin: 49 39 e2 + [-,%rflags] v41 = ifcmp_sp v2 ; bin: 49 39 e2 ; asm: cmpq $-100, %rcx - [-,%eflags] v522 = ifcmp_imm v1, -100 ; bin: 48 83 f9 9c + [-,%rflags] v522 = ifcmp_imm v1, -100 ; bin: 48 83 f9 9c ; asm: cmpq $100, %r10 - [-,%eflags] v523 = ifcmp_imm v2, 100 ; bin: 49 83 fa 64 + [-,%rflags] v523 = ifcmp_imm v2, 100 ; bin: 49 83 fa 64 ; asm: cmpq $-10000, %rcx - [-,%eflags] v524 = ifcmp_imm v1, -10000 ; bin: 48 81 f9 ffffd8f0 + [-,%rflags] v524 = ifcmp_imm v1, -10000 ; bin: 48 81 f9 ffffd8f0 ; asm: cmpq $10000, %r10 - [-,%eflags] v525 = ifcmp_imm v2, 10000 ; bin: 49 81 fa 00002710 + [-,%rflags] v525 = ifcmp_imm v2, 10000 ; bin: 49 81 fa 00002710 return @@ -1055,19 +1055,19 @@ ebb0: regfill v1, ss1 -> %rcx ; bin: 8b 8c 24 00000408 ; asm: cmpl %esi, %ecx - [-,%eflags] v520 = ifcmp v1, v2 ; bin: 39 f1 + [-,%rflags] v520 = ifcmp v1, v2 ; bin: 39 f1 ; asm: cmpl %r10d, %esi - [-,%eflags] v521 = ifcmp v2, v3 ; bin: 44 39 d6 + [-,%rflags] v521 = ifcmp v2, v3 ; bin: 44 39 d6 ; asm: cmpl $-100, %ecx - [-,%eflags] v522 = ifcmp_imm v1, -100 ; bin: 83 f9 9c + [-,%rflags] v522 = ifcmp_imm v1, -100 ; bin: 83 f9 9c ; asm: cmpl $100, %r10d - [-,%eflags] v523 = ifcmp_imm v3, 100 ; bin: 41 83 fa 64 + [-,%rflags] v523 = ifcmp_imm v3, 100 ; bin: 41 83 fa 64 ; asm: cmpl $-10000, %ecx - [-,%eflags] v524 = ifcmp_imm v1, -10000 ; bin: 81 f9 ffffd8f0 + [-,%rflags] v524 = ifcmp_imm v1, -10000 ; bin: 81 f9 ffffd8f0 ; asm: cmpl $10000, %r10d - [-,%eflags] v525 = ifcmp_imm v3, 10000 ; bin: 41 81 fa 00002710 + [-,%rflags] v525 = ifcmp_imm v3, 10000 ; bin: 41 81 fa 00002710 ; asm: shll $2, %esi [-,%rsi] v526 = ishl_imm v2, 2 ; bin: c1 e6 02 diff --git a/lib/cretonne/meta/isa/intel/recipes.py b/lib/cretonne/meta/isa/intel/recipes.py index 9d015a25bb..5c37677f14 100644 --- a/lib/cretonne/meta/isa/intel/recipes.py +++ b/lib/cretonne/meta/isa/intel/recipes.py @@ -281,7 +281,7 @@ trap = TailRecipe( # Macro: conditional jump over a ud2. trapif = EncRecipe( - 'trapif', IntCondTrap, size=4, ins=FLAG.eflags, outs=(), + 'trapif', IntCondTrap, size=4, ins=FLAG.rflags, outs=(), clobbers_flags=False, emit=''' // Jump over a 2-byte ud2. @@ -293,7 +293,7 @@ trapif = EncRecipe( ''') trapff = EncRecipe( - 'trapff', FloatCondTrap, size=4, ins=FLAG.eflags, outs=(), + 'trapff', FloatCondTrap, size=4, ins=FLAG.rflags, outs=(), clobbers_flags=False, instp=floatccs(FloatCondTrap), emit=''' @@ -985,7 +985,7 @@ jmpd = TailRecipe( ''') brib = TailRecipe( - 'brib', BranchInt, size=1, ins=FLAG.eflags, outs=(), + 'brib', BranchInt, size=1, ins=FLAG.rflags, outs=(), branch_range=8, clobbers_flags=False, emit=''' @@ -994,7 +994,7 @@ brib = TailRecipe( ''') brid = TailRecipe( - 'brid', BranchInt, size=4, ins=FLAG.eflags, outs=(), + 'brid', BranchInt, size=4, ins=FLAG.rflags, outs=(), branch_range=32, clobbers_flags=False, emit=''' @@ -1003,7 +1003,7 @@ brid = TailRecipe( ''') brfb = TailRecipe( - 'brfb', BranchFloat, size=1, ins=FLAG.eflags, outs=(), + 'brfb', BranchFloat, size=1, ins=FLAG.rflags, outs=(), branch_range=8, clobbers_flags=False, instp=floatccs(BranchFloat), @@ -1013,7 +1013,7 @@ brfb = TailRecipe( ''') brfd = TailRecipe( - 'brfd', BranchFloat, size=4, ins=FLAG.eflags, outs=(), + 'brfd', BranchFloat, size=4, ins=FLAG.rflags, outs=(), branch_range=32, clobbers_flags=False, instp=floatccs(BranchFloat), @@ -1033,7 +1033,7 @@ brfd = TailRecipe( # seti = TailRecipe( - 'seti', IntCond, size=1, ins=FLAG.eflags, outs=GPR, + 'seti', IntCond, size=1, ins=FLAG.rflags, outs=GPR, requires_prefix=True, clobbers_flags=False, emit=''' @@ -1041,7 +1041,7 @@ seti = TailRecipe( modrm_r_bits(out_reg0, bits, sink); ''') seti_abcd = TailRecipe( - 'seti_abcd', IntCond, size=1, ins=FLAG.eflags, outs=ABCD, + 'seti_abcd', IntCond, size=1, ins=FLAG.rflags, outs=ABCD, when_prefixed=seti, clobbers_flags=False, emit=''' @@ -1050,7 +1050,7 @@ seti_abcd = TailRecipe( ''') setf = TailRecipe( - 'setf', FloatCond, size=1, ins=FLAG.eflags, outs=GPR, + 'setf', FloatCond, size=1, ins=FLAG.rflags, outs=GPR, requires_prefix=True, clobbers_flags=False, emit=''' @@ -1058,7 +1058,7 @@ setf = TailRecipe( modrm_r_bits(out_reg0, bits, sink); ''') setf_abcd = TailRecipe( - 'setf_abcd', FloatCond, size=1, ins=FLAG.eflags, outs=ABCD, + 'setf_abcd', FloatCond, size=1, ins=FLAG.rflags, outs=ABCD, when_prefixed=setf, clobbers_flags=False, emit=''' @@ -1072,7 +1072,7 @@ setf_abcd = TailRecipe( # 1 byte, modrm(r,r), is after the opcode # cmov = TailRecipe( - 'cmov', IntSelect, size=1, ins=(FLAG.eflags, GPR, GPR), outs=2, + 'cmov', IntSelect, size=1, ins=(FLAG.rflags, GPR, GPR), outs=2, requires_prefix=False, clobbers_flags=False, emit=''' @@ -1084,7 +1084,7 @@ cmov = TailRecipe( # Bit scan forwards and reverse # bsf_and_bsr = TailRecipe( - 'bsf_and_bsr', Unary, size=1, ins=GPR, outs=(GPR, FLAG.eflags), + 'bsf_and_bsr', Unary, size=1, ins=GPR, outs=(GPR, FLAG.rflags), requires_prefix=False, clobbers_flags=True, emit=''' @@ -1098,7 +1098,7 @@ bsf_and_bsr = TailRecipe( # XX /r, MR form. Compare two GPR registers and set flags. rcmp = TailRecipe( - 'rcmp', Binary, size=1, ins=(GPR, GPR), outs=FLAG.eflags, + 'rcmp', Binary, size=1, ins=(GPR, GPR), outs=FLAG.rflags, emit=''' PUT_OP(bits, rex2(in_reg0, in_reg1), sink); modrm_rr(in_reg0, in_reg1, sink); @@ -1106,7 +1106,7 @@ rcmp = TailRecipe( # XX /r, RM form. Compare two FPR registers and set flags. fcmp = TailRecipe( - 'fcmp', Binary, size=1, ins=(FPR, FPR), outs=FLAG.eflags, + 'fcmp', Binary, size=1, ins=(FPR, FPR), outs=FLAG.rflags, emit=''' PUT_OP(bits, rex2(in_reg1, in_reg0), sink); modrm_rr(in_reg1, in_reg0, sink); @@ -1114,7 +1114,7 @@ fcmp = TailRecipe( # XX /n, MI form with imm8. rcmpib = TailRecipe( - 'rcmpib', BinaryImm, size=2, ins=GPR, outs=FLAG.eflags, + 'rcmpib', BinaryImm, size=2, ins=GPR, outs=FLAG.rflags, instp=IsSignedInt(BinaryImm.imm, 8), emit=''' PUT_OP(bits, rex1(in_reg0), sink); @@ -1125,7 +1125,7 @@ rcmpib = TailRecipe( # XX /n, MI form with imm32. rcmpid = TailRecipe( - 'rcmpid', BinaryImm, size=5, ins=GPR, outs=FLAG.eflags, + 'rcmpid', BinaryImm, size=5, ins=GPR, outs=FLAG.rflags, instp=IsSignedInt(BinaryImm.imm, 32), emit=''' PUT_OP(bits, rex1(in_reg0), sink); @@ -1136,7 +1136,7 @@ rcmpid = TailRecipe( # Same as rcmp, but second operand is the stack pointer. rcmp_sp = TailRecipe( - 'rcmp_sp', Unary, size=1, ins=GPR, outs=FLAG.eflags, + 'rcmp_sp', Unary, size=1, ins=GPR, outs=FLAG.rflags, emit=''' PUT_OP(bits, rex2(in_reg0, RU::rsp.into()), sink); modrm_rr(in_reg0, RU::rsp.into(), sink); @@ -1302,7 +1302,7 @@ icscc = TailRecipe( # Same thing for floating point. # -# The ucomiss/ucomisd instructions set the EFLAGS bits CF/PF/CF like this: +# The ucomiss/ucomisd instructions set the FLAGS bits CF/PF/CF like this: # # ZPC OSA # UN 111 000 diff --git a/lib/cretonne/meta/isa/intel/registers.py b/lib/cretonne/meta/isa/intel/registers.py index 354001a102..a4832640cd 100644 --- a/lib/cretonne/meta/isa/intel/registers.py +++ b/lib/cretonne/meta/isa/intel/registers.py @@ -43,7 +43,7 @@ FlagRegs = RegBank( 'Flag registers', units=1, pressure_tracking=False, - names=['eflags']) + names=['rflags']) GPR = RegClass(IntRegs) # Certain types of deref encodings cannot be used with all registers. diff --git a/lib/cretonne/src/isa/intel/binemit.rs b/lib/cretonne/src/isa/intel/binemit.rs index 2d045a0882..ddd3405e18 100644 --- a/lib/cretonne/src/isa/intel/binemit.rs +++ b/lib/cretonne/src/isa/intel/binemit.rs @@ -257,7 +257,7 @@ fn icc2opc(cond: IntCC) -> u16 { /// Get the low 4 bits of an opcode for a floating point condition code. /// -/// The ucomiss/ucomisd instructions set the EFLAGS bits CF/PF/CF like this: +/// The ucomiss/ucomisd instructions set the FLAGS bits CF/PF/CF like this: /// /// ZPC OSA /// UN 111 000