Merge pull request #2966 from akirilov-arm/simd_int_to_int_extend

Enable the simd_int_to_int_extend test for AArch64

build.rs

@@ -238,8 +238,7 @@ fn ignore(testsuite: &str, testname: &str, strategy: &str) -> bool {
             | ("simd", "simd_i32x4_extadd_pairwise_i16x8")
             | ("simd", "simd_i32x4_extmul_i16x8")
             | ("simd", "simd_i32x4_trunc_sat_f64x2")
-            | ("simd", "simd_i64x2_extmul_i32x4")
+            | ("simd", "simd_i64x2_extmul_i32x4") => return true,
-            | ("simd", "simd_int_to_int_extend") => return true,
 
             _ => {}
         },

cranelift/codegen/meta/src/shared/instructions.rs

@@ -4009,18 +4009,18 @@ pub(crate) fn define(
         .operands_out(vec![a]),
     );
 
-    let I8or16xN = &TypeVar::new(
+    let I8or16or32xN = &TypeVar::new(
-        "I8or16xN",
+        "I8or16or32xN",
-        "A SIMD vector type containing integer lanes 8 or 16 bits wide.",
+        "A SIMD vector type containing integer lanes 8, 16, or 32 bits wide.",
         TypeSetBuilder::new()
-            .ints(8..16)
+            .ints(8..32)
-            .simd_lanes(8..16)
+            .simd_lanes(4..16)
             .includes_scalars(false)
             .build(),
     );
 
-    let x = &Operand::new("x", I8or16xN);
+    let x = &Operand::new("x", I8or16or32xN);
-    let a = &Operand::new("a", &I8or16xN.merge_lanes());
+    let a = &Operand::new("a", &I8or16or32xN.merge_lanes());
 
     ig.push(
         Inst::new(

cranelift/codegen/src/isa/aarch64/lower_inst.rs

@@ -3175,6 +3175,10 @@ pub(crate) fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
                 (I32, Opcode::SwidenHigh) => (VecExtendOp::Sxtl16, true),
                 (I32, Opcode::UwidenLow) => (VecExtendOp::Uxtl16, false),
                 (I32, Opcode::UwidenHigh) => (VecExtendOp::Uxtl16, true),
+                (I64, Opcode::SwidenLow) => (VecExtendOp::Sxtl32, false),
+                (I64, Opcode::SwidenHigh) => (VecExtendOp::Sxtl32, true),
+                (I64, Opcode::UwidenLow) => (VecExtendOp::Uxtl32, false),
+                (I64, Opcode::UwidenHigh) => (VecExtendOp::Uxtl32, true),
                 _ => {
                     return Err(CodegenError::Unsupported(format!(
                         "Unsupported SIMD vector lane type: {:?}",

cranelift/wasm/src/code_translator.rs

@@ -1843,7 +1843,22 @@ pub fn translate_operator<FE: FuncEnvironment + ?Sized>(
             let a = pop1_with_bitcast(state, I16X8, builder);
             state.push1(builder.ins().uwiden_high(a))
         }
-
+        Operator::I64x2ExtendLowI32x4S => {
+            let a = pop1_with_bitcast(state, I32X4, builder);
+            state.push1(builder.ins().swiden_low(a))
+        }
+        Operator::I64x2ExtendHighI32x4S => {
+            let a = pop1_with_bitcast(state, I32X4, builder);
+            state.push1(builder.ins().swiden_high(a))
+        }
+        Operator::I64x2ExtendLowI32x4U => {
+            let a = pop1_with_bitcast(state, I32X4, builder);
+            state.push1(builder.ins().uwiden_low(a))
+        }
+        Operator::I64x2ExtendHighI32x4U => {
+            let a = pop1_with_bitcast(state, I32X4, builder);
+            state.push1(builder.ins().uwiden_high(a))
+        }
         Operator::F32x4Ceil | Operator::F64x2Ceil => {
             // This is something of a misuse of `type_of`, because that produces the return type
             // of `op`.  In this case we want the arg type, but we know it's the same as the
@@ -1871,11 +1886,7 @@ pub fn translate_operator<FE: FuncEnvironment + ?Sized>(
             let arg = pop1_with_bitcast(state, type_of(op), builder);
             state.push1(builder.ins().popcnt(arg));
         }
-        Operator::I64x2ExtendLowI32x4S
+        Operator::I16x8Q15MulrSatS
-        | Operator::I64x2ExtendHighI32x4S
-        | Operator::I64x2ExtendLowI32x4U
-        | Operator::I64x2ExtendHighI32x4U
-        | Operator::I16x8Q15MulrSatS
         | Operator::I16x8ExtMulLowI8x16S
         | Operator::I16x8ExtMulHighI8x16S
         | Operator::I16x8ExtMulLowI8x16U