diff --git a/lib/cretonne/meta/isa/intel/recipes.py b/lib/cretonne/meta/isa/intel/recipes.py
index 3b9b508ce4..313ca7abd6 100644
--- a/lib/cretonne/meta/isa/intel/recipes.py
+++ b/lib/cretonne/meta/isa/intel/recipes.py
@@ -12,8 +12,8 @@ from base.formats import Jump, Branch, BranchInt, BranchFloat
 from base.formats import Ternary, FuncAddr, UnaryGlobalVar
 from base.formats import RegMove, RegSpill, RegFill, CopySpecial
 from .registers import GPR, ABCD, FPR, GPR_DEREF_SAFE, GPR_ZERO_DEREF_SAFE
-from .registers import GPR8, FPR8, GPR8_ZERO_DEREF_SAFE, FLAG, StackGPR32
-from .registers import StackFPR32
+from .registers import GPR8, FPR8, GPR8_DEREF_SAFE, GPR8_ZERO_DEREF_SAFE, FLAG
+from .registers import StackGPR32, StackFPR32
 from .defs import supported_floatccs
 from .settings import use_sse41
 
@@ -105,7 +105,7 @@ def replace_put_op(emit, prefix):
 # Register class mapping for no-REX instructions.
 NOREX_MAP = {
         GPR: GPR8,
-        GPR_DEREF_SAFE: GPR8,
+        GPR_DEREF_SAFE: GPR8_DEREF_SAFE,
         GPR_ZERO_DEREF_SAFE: GPR8_ZERO_DEREF_SAFE,
         FPR: FPR8
     }
diff --git a/lib/cretonne/meta/isa/intel/registers.py b/lib/cretonne/meta/isa/intel/registers.py
index ef7b5c6d97..354001a102 100644
--- a/lib/cretonne/meta/isa/intel/registers.py
+++ b/lib/cretonne/meta/isa/intel/registers.py
@@ -49,10 +49,11 @@ GPR = RegClass(IntRegs)
 # Certain types of deref encodings cannot be used with all registers.
 #   R13/RBP cannot be used with zero-offset load or store instructions.
 #   R12 cannot be used with a non-SIB-byte encoding of all derefs.
-GPR_DEREF_SAFE = GPR.without(GPR.r12)
+GPR_DEREF_SAFE = GPR.without(GPR.rsp, GPR.r12)
 GPR_ZERO_DEREF_SAFE = GPR_DEREF_SAFE.without(GPR.rbp, GPR.r13)
 GPR8 = GPR[0:8]
-GPR8_ZERO_DEREF_SAFE = GPR8.without(GPR.rbp)
+GPR8_DEREF_SAFE = GPR8.without(GPR.rsp)
+GPR8_ZERO_DEREF_SAFE = GPR8_DEREF_SAFE.without(GPR.rbp)
 ABCD = GPR[0:4]
 FPR = RegClass(FloatRegs)
 FPR8 = FPR[0:8]