Add x86 SIMD legalizations for integer greater-than

This includes `icmp ugt`, `icmp sge`, and `icmp uge` for vectors with lanes of I8, I16, and I32.

cranelift/filetests/filetests/isa/x86/simd-comparison-legalize.clif

@@ -10,3 +10,27 @@ ebb0(v0: i32x4, v1: i32x4):
     ; nextln: v2 = bxor v4, v3
     return v2
 }
+
+function %icmp_ugt_i32x4(i32x4, i32x4) -> b32x4 {
+ebb0(v0: i32x4, v1: i32x4):
+    v2 = icmp ugt v0, v1
+    ; check: v3 = x86_pmaxu v0, v1
+    ; nextln: v2 = icmp eq v0, v3
+    return v2
+}
+
+function %icmp_sge_i16x8(i16x8, i16x8) -> b16x8 {
+ebb0(v0: i16x8, v1: i16x8):
+    v2 = icmp sge v0, v1
+    ; check: v3 = x86_pmins v0, v1
+    ; nextln: v2 = icmp eq v3, v1
+    return v2
+}
+
+function %icmp_uge_i8x16(i8x16, i8x16) -> b8x16 {
+ebb0(v0: i8x16, v1: i8x16):
+    v2 = icmp uge v0, v1
+    ; check: v3 = x86_pminu v0, v1
+    ; nextln: v2 = icmp eq v3, v1
+    return v2
+}

cranelift/filetests/filetests/isa/x86/simd-comparison-run.clif

@@ -107,3 +107,33 @@ ebb0:
     return v8
 }
 ; run
+
+function %icmp_ugt_i8x16() -> b1 {
+ebb0:
+    v0 = vconst.i8x16 [1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16]
+    v1 = vconst.i8x16 [0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1]
+    v2 = icmp ugt v0, v1
+    v8 = vall_true v2
+    return v8
+}
+; run
+
+function %icmp_sge_i16x8() -> b1 {
+ebb0:
+    v0 = vconst.i16x8 [-1 1 2 3 4 5 6 7]
+    v1 = vconst.i16x8 [-1 1 1 1 1 1 1 1]
+    v2 = icmp sge v0, v1
+    v8 = vall_true v2
+    return v8
+}
+; run
+
+function %icmp_uge_i32x4() -> b1 {
+ebb0:
+    v0 = vconst.i32x4 [1 2 3 4]
+    v1 = vconst.i32x4 [1 1 1 1]
+    v2 = icmp uge v0, v1
+    v8 = vall_true v2
+    return v8
+}
+; run