From fe7dd41435a1d826dd14cb4163e574b6b831791c Mon Sep 17 00:00:00 2001
From: Benjamin Bouvier <public@benj.me>
Date: Mon, 6 Jul 2020 14:45:15 +0200
Subject: [PATCH] machinst x64: fix iconst emission

---
 cranelift/codegen/src/isa/x64/inst/mod.rs | 21 ++++++++++++---------
 cranelift/codegen/src/isa/x64/lower.rs    | 15 +++------------
 2 files changed, 15 insertions(+), 21 deletions(-)

diff --git a/cranelift/codegen/src/isa/x64/inst/mod.rs b/cranelift/codegen/src/isa/x64/inst/mod.rs
index d4b0e3eace..d4f3bb4079 100644
--- a/cranelift/codegen/src/isa/x64/inst/mod.rs
+++ b/cranelift/codegen/src/isa/x64/inst/mod.rs
@@ -273,15 +273,13 @@ pub enum Inst {
     VirtualSPOffsetAdj { offset: i64 },
 }
 
-// Handy constructors for Insts.
-
-// For various sizes, will some number of lowest bits sign extend to be the
-// same as the whole value?
-pub(crate) fn low32willSXto64(x: u64) -> bool {
+pub(crate) fn low32_will_sign_extend_to_64(x: u64) -> bool {
     let xs = x as i64;
     xs == ((xs << 32) >> 32)
 }
 
+// Handy constructors for Insts.
+
 impl Inst {
     pub(crate) fn nop(len: u8) -> Self {
         debug_assert!(len <= 16);
@@ -337,7 +335,11 @@ impl Inst {
     pub(crate) fn imm_r(dst_is_64: bool, simm64: u64, dst: Writable<Reg>) -> Inst {
         debug_assert!(dst.to_reg().get_class() == RegClass::I64);
         if !dst_is_64 {
-            debug_assert!(low32willSXto64(simm64));
+            debug_assert!(
+                low32_will_sign_extend_to_64(simm64),
+                "{} won't sign-extend to 64 bits!",
+                simm64
+            );
         }
         Inst::Imm_R {
             dst_is_64,
@@ -1309,10 +1311,11 @@ impl MachInst for Inst {
         Inst::jmp_known(BranchTarget::Label(label))
     }
 
-    fn gen_constant(to_reg: Writable<Reg>, value: u64, _: Type) -> SmallVec<[Self; 4]> {
+    fn gen_constant(to_reg: Writable<Reg>, value: u64, ty: Type) -> SmallVec<[Self; 4]> {
         let mut ret = SmallVec::new();
-        let is64 = value > 0xffff_ffff;
-        ret.push(Inst::imm_r(is64, value, to_reg));
+        debug_assert!(ty.is_int(), "float constants NYI");
+        let is_64 = ty == I64 && value > 0x7fffffff;
+        ret.push(Inst::imm_r(is_64, value, to_reg));
         ret
     }
 
diff --git a/cranelift/codegen/src/isa/x64/lower.rs b/cranelift/codegen/src/isa/x64/lower.rs
index 6a0abd5c7b..2f7aa6774d 100644
--- a/cranelift/codegen/src/isa/x64/lower.rs
+++ b/cranelift/codegen/src/isa/x64/lower.rs
@@ -234,9 +234,7 @@ fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
     match op {
         Opcode::Iconst => {
             if let Some(w64) = iri_to_u64_imm(ctx, insn) {
-                // Get exactly the bit pattern in 'w64' into the dest.  No
-                // monkeying with sign extension etc.
-                let dst_is_64 = w64 > 0xFFFF_FFFF;
+                let dst_is_64 = w64 > 0x7fffffff;
                 let dst = output_to_reg(ctx, outputs[0]);
                 ctx.emit(Inst::imm_r(dst_is_64, w64, dst));
             } else {
@@ -421,15 +419,8 @@ fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
             for i in 0..ctx.num_inputs(insn) {
                 let src_reg = input_to_reg(ctx, inputs[i]);
                 let retval_reg = ctx.retval(i);
-                if src_reg.get_class() == RegClass::I64 {
-                    ctx.emit(Inst::mov_r_r(true, src_reg, retval_reg));
-                } else if src_reg.get_class() == RegClass::V128 {
-                    ctx.emit(Inst::xmm_mov_rm_r(
-                        SseOpcode::Movsd,
-                        RegMem::reg(src_reg),
-                        retval_reg,
-                    ));
-                }
+                let ty = ctx.input_ty(insn, i);
+                ctx.emit(Inst::gen_move(retval_reg, src_reg, ty));
             }
             // N.B.: the Ret itself is generated by the ABI.
         }