Perform I-Cache Maintenance on RISC-V (#5698)

* re modify this.

* fix compile failure.

* fix unused warning.

crates/jit-icache-coherence/Cargo.toml

@@ -21,3 +21,11 @@ features = [
 
 [target.'cfg(any(target_os = "linux", target_os = "macos", target_os = "freebsd", target_os = "android"))'.dependencies]
 libc = "0.2.42"
+
+[features]
+# Most modern CPUs are SMP (multicore). However, when only one core is present,
+# some aspects of coherence are much cheaper. For example, RISC-V can use
+# one instruction `fence.i` rather than a syscall that invokes all other cores.
+# This feature enables such optimizations, but the resulting program will *only*
+# be safe to run on one-core systems.
+one-core = []