Add vsplit and vconcat instructions.

Add support for two new type variable functions: half_vector() and
double_vector().

Use these two instructions to break down unsupported SIMD types and
build them up again.

lib/cretonne/src/ir/instructions.rs

@@ -708,6 +708,12 @@ enum OperandConstraint {
 
     /// This operand is `ctrlType.double_width()`.
     DoubleWidth,
+
+    /// This operand is `ctrlType.half_vector()`.
+    HalfVector,
+
+    /// This operand is `ctrlType.double_vector()`.
+    DoubleVector,
 }
 
 impl OperandConstraint {
@@ -725,6 +731,8 @@ impl OperandConstraint {
             AsBool => Some(ctrl_type.as_bool()),
             HalfWidth => Some(ctrl_type.half_width().expect("invalid type for half_width")),
             DoubleWidth => Some(ctrl_type.double_width().expect("invalid type for double_width")),
+            HalfVector => Some(ctrl_type.half_vector().expect("invalid type for half_vector")),
+            DoubleVector => Some(ctrl_type.by(2).expect("invalid type for double_vector")),
         }
     }
 }

lib/cretonne/src/ir/types.rs

@@ -217,6 +217,8 @@ impl Type {
     }
 
     /// Get a SIMD vector with half the number of lanes.
+    ///
+    /// There is no `double_vector()` method. Use `t.by(2)` instead.
     pub fn half_vector(self) -> Option<Type> {
         if self.is_scalar() {
             None