Add x86 pack instructions
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@@ -6,7 +6,6 @@ use crate::cdsl::instructions::{
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use crate::cdsl::operands::Operand;
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use crate::cdsl::types::ValueType;
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use crate::cdsl::typevar::{Interval, TypeSetBuilder, TypeVar};
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use crate::shared::entities::EntityRefs;
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use crate::shared::formats::Formats;
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use crate::shared::immediates::Immediates;
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@@ -275,7 +274,7 @@ pub(crate) fn define(
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);
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let a = &Operand::new("a", TxN).with_doc("A vector value (i.e. held in an XMM register)");
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let b = &Operand::new("b", TxN).with_doc("A vector value (i.e. held in an XMM register)");
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let i = &Operand::new("i", uimm8,).with_doc( "An ordering operand controlling the copying of data from the source to the destination; see PSHUFD in Intel manual for details");
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let i = &Operand::new("i", uimm8).with_doc("An ordering operand controlling the copying of data from the source to the destination; see PSHUFD in Intel manual for details");
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ig.push(
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Inst::new(
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@@ -410,6 +409,35 @@ pub(crate) fn define(
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.operands_out(vec![a]),
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);
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let I16xN = &TypeVar::new(
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"I16xN",
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"A SIMD vector type containing integers 16-bits wide and up",
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TypeSetBuilder::new()
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.ints(16..32)
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.simd_lanes(4..8)
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.includes_scalars(false)
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.build(),
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);
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let x = &Operand::new("x", I16xN);
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let y = &Operand::new("y", I16xN);
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let a = &Operand::new("a", &I16xN.split_lanes());
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ig.push(
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Inst::new(
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"x86_packss",
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r#"
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Convert packed signed integers the lanes of ``x`` and ``y`` into half-width integers, using
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signed saturation to handle overflows. For example, with notional i16x2 vectors, where
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``x = [x1, x0]`` and ``y = [y1, y0]``, this operation would result in
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``a = [y1', y0', x1', x0']`` (using the Intel manual's right-to-left lane ordering).
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"#,
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&formats.binary,
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)
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.operands_in(vec![x, y])
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.operands_out(vec![a]),
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);
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let x = &Operand::new("x", FxN);
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let y = &Operand::new("y", FxN);
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let a = &Operand::new("a", FxN);
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