Fill in boilerplate for Intel and ARM targets.

The intel, arm32, and arm32 targets were only defined in the meta
language previously. Add Rust implementations too.

This is mostly boilerplate, except for the unit tests in the
registers.rs files.

lib/cretonne/src/isa/mod.rs

@@ -46,6 +46,9 @@ use settings;
 use ir::{InstructionData, DataFlowGraph};
 
 pub mod riscv;
+pub mod intel;
+pub mod arm32;
+pub mod arm64;
 mod encoding;
 mod enc_tables;
 mod registers;
@@ -55,6 +58,9 @@ mod registers;
 pub fn lookup(name: &str) -> Option<Builder> {
     match name {
         "riscv" => riscv_builder(),
+        "intel" => intel_builder(),
+        "arm32" => arm32_builder(),
+        "arm64" => arm64_builder(),
         _ => None,
     }
 }
@@ -64,6 +70,18 @@ fn riscv_builder() -> Option<Builder> {
     Some(riscv::isa_builder())
 }
 
+fn intel_builder() -> Option<Builder> {
+    Some(intel::isa_builder())
+}
+
+fn arm32_builder() -> Option<Builder> {
+    Some(arm32::isa_builder())
+}
+
+fn arm64_builder() -> Option<Builder> {
+    Some(arm64::isa_builder())
+}
+
 /// Builder for a `TargetIsa`.
 /// Modify the ISA-specific settings before creating the `TargetIsa` trait object with `finish`.
 pub struct Builder {