Fill in boilerplate for Intel and ARM targets.

The intel, arm32, and arm32 targets were only defined in the meta
language previously. Add Rust implementations too.

This is mostly boilerplate, except for the unit tests in the
registers.rs files.

lib/cretonne/src/isa/arm64/enc_tables.rs

@@ -0,0 +1,8 @@
+//! Encoding tables for ARM64 ISA.
+
+use ir::InstructionData;
+use ir::instructions::InstructionFormat;
+use ir::types;
+use isa::enc_tables::{Level1Entry, Level2Entry};
+
+include!(concat!(env!("OUT_DIR"), "/encoding-arm64.rs"));

lib/cretonne/src/isa/arm64/mod.rs

@@ -0,0 +1,66 @@
+//! ARM 64-bit Instruction Set Architecture.
+
+pub mod settings;
+mod enc_tables;
+mod registers;
+
+use super::super::settings as shared_settings;
+use isa::enc_tables::{lookup_enclist, general_encoding};
+use isa::Builder as IsaBuilder;
+use isa::{TargetIsa, RegInfo, Encoding, Legalize};
+use ir::{InstructionData, DataFlowGraph};
+
+#[allow(dead_code)]
+struct Isa {
+    shared_flags: shared_settings::Flags,
+    isa_flags: settings::Flags,
+}
+
+/// Get an ISA builder for creating ARM64 targets.
+pub fn isa_builder() -> IsaBuilder {
+    IsaBuilder {
+        setup: settings::builder(),
+        constructor: isa_constructor,
+    }
+}
+
+fn isa_constructor(shared_flags: shared_settings::Flags,
+                   builder: &shared_settings::Builder)
+                   -> Box<TargetIsa> {
+    Box::new(Isa {
+        isa_flags: settings::Flags::new(&shared_flags, builder),
+        shared_flags: shared_flags,
+    })
+}
+
+impl TargetIsa for Isa {
+    fn name(&self) -> &'static str {
+        "arm64"
+    }
+
+    fn flags(&self) -> &shared_settings::Flags {
+        &self.shared_flags
+    }
+
+    fn register_info(&self) -> &RegInfo {
+        &registers::INFO
+    }
+
+    fn encode(&self, _: &DataFlowGraph, inst: &InstructionData) -> Result<Encoding, Legalize> {
+        lookup_enclist(inst.first_type(),
+                       inst.opcode(),
+                       &enc_tables::LEVEL1_A64[..],
+                       &enc_tables::LEVEL2[..])
+            .and_then(|enclist_offset| {
+                general_encoding(enclist_offset,
+                                 &enc_tables::ENCLISTS[..],
+                                 |instp| enc_tables::check_instp(inst, instp),
+                                 |isap| self.isa_flags.numbered_predicate(isap as usize))
+                    .ok_or(Legalize::Expand)
+            })
+    }
+
+    fn recipe_names(&self) -> &'static [&'static str] {
+        &enc_tables::RECIPE_NAMES[..]
+    }
+}

lib/cretonne/src/isa/arm64/registers.rs

@@ -0,0 +1,37 @@
+//! ARM64 register descriptions.
+
+use isa::registers::{RegBank, RegInfo};
+
+include!(concat!(env!("OUT_DIR"), "/registers-arm64.rs"));
+
+#[cfg(test)]
+mod tests {
+    use super::INFO;
+    use isa::RegUnit;
+
+    #[test]
+    fn unit_encodings() {
+        assert_eq!(INFO.parse_regunit("x0"), Some(0));
+        assert_eq!(INFO.parse_regunit("x31"), Some(31));
+        assert_eq!(INFO.parse_regunit("v0"), Some(32));
+        assert_eq!(INFO.parse_regunit("v31"), Some(63));
+
+        assert_eq!(INFO.parse_regunit("x32"), None);
+        assert_eq!(INFO.parse_regunit("v32"), None);
+    }
+
+    #[test]
+    fn unit_names() {
+        fn uname(ru: RegUnit) -> String {
+            INFO.display_regunit(ru).to_string()
+        }
+
+        assert_eq!(uname(0), "%x0");
+        assert_eq!(uname(1), "%x1");
+        assert_eq!(uname(31), "%x31");
+        assert_eq!(uname(32), "%v0");
+        assert_eq!(uname(33), "%v1");
+        assert_eq!(uname(63), "%v31");
+        assert_eq!(uname(64), "%INVALID64");
+    }
+}

lib/cretonne/src/isa/arm64/settings.rs

@@ -0,0 +1,9 @@
+//! ARM64 Settings.
+
+use settings::{self, detail, Builder};
+use std::fmt;
+
+// Include code generated by `lib/cretonne/meta/gen_settings.py`. This file contains a public
+// `Flags` struct with an impl for all of the settings defined in
+// `lib/cretonne/meta/cretonne/settings.py`.
+include!(concat!(env!("OUT_DIR"), "/settings-arm64.rs"));