Fill in boilerplate for Intel and ARM targets.

The intel, arm32, and arm32 targets were only defined in the meta
language previously. Add Rust implementations too.

This is mostly boilerplate, except for the unit tests in the
registers.rs files.

lib/cretonne/meta/isa/arm32/registers.py

@@ -6,15 +6,7 @@ from cdsl.registers import RegBank, RegClass
 from .defs import ISA
 
 
-# Special register units:
-# - r15 is the program counter.
-# - r14 is the link register.
-# - r13 is usually the stack pointer.
-IntRegs = RegBank(
-        'IntRegs', ISA,
-        'General purpose registers',
-        units=16, prefix='r')
-
+# Define the larger float bank first to avoid the alignment gap.
 FloatRegs = RegBank(
         'FloatRegs', ISA, r"""
         Floating point registers.
@@ -28,6 +20,15 @@ FloatRegs = RegBank(
         """,
         units=64, prefix='s')
 
+# Special register units:
+# - r15 is the program counter.
+# - r14 is the link register.
+# - r13 is usually the stack pointer.
+IntRegs = RegBank(
+        'IntRegs', ISA,
+        'General purpose registers',
+        units=16, prefix='r')
+
 GPR = RegClass('GPR', IntRegs)
 S = RegClass('S', FloatRegs, count=32)
 D = RegClass('D', FloatRegs, width=2)