Fill in boilerplate for Intel and ARM targets.

The intel, arm32, and arm32 targets were only defined in the meta
language previously. Add Rust implementations too.

This is mostly boilerplate, except for the unit tests in the
registers.rs files.

lib/cretonne/meta/isa/arm32/__init__.py

@@ -8,7 +8,7 @@ This target ISA generates code for ARMv7 and ARMv8 CPUs in 32-bit mode
 
 from __future__ import absolute_import
 from . import defs
-from . import registers  # noqa
+from . import settings, registers  # noqa
 
 # Re-export the primary target ISA definition.
 ISA = defs.ISA.finish()

lib/cretonne/meta/isa/arm32/registers.py

@@ -6,15 +6,7 @@ from cdsl.registers import RegBank, RegClass
 from .defs import ISA
 
 
-# Special register units:
-# - r15 is the program counter.
-# - r14 is the link register.
-# - r13 is usually the stack pointer.
-IntRegs = RegBank(
-        'IntRegs', ISA,
-        'General purpose registers',
-        units=16, prefix='r')
-
+# Define the larger float bank first to avoid the alignment gap.
 FloatRegs = RegBank(
         'FloatRegs', ISA, r"""
         Floating point registers.
@@ -28,6 +20,15 @@ FloatRegs = RegBank(
         """,
         units=64, prefix='s')
 
+# Special register units:
+# - r15 is the program counter.
+# - r14 is the link register.
+# - r13 is usually the stack pointer.
+IntRegs = RegBank(
+        'IntRegs', ISA,
+        'General purpose registers',
+        units=16, prefix='r')
+
 GPR = RegClass('GPR', IntRegs)
 S = RegClass('S', FloatRegs, count=32)
 D = RegClass('D', FloatRegs, width=2)

lib/cretonne/meta/isa/arm32/settings.py

@@ -0,0 +1,11 @@
+"""
+ARM32 settings.
+"""
+from __future__ import absolute_import
+from cdsl.settings import SettingGroup
+import base.settings as shared
+from .defs import ISA
+
+ISA.settings = SettingGroup('arm32', parent=shared.group)
+
+ISA.settings.close(globals())

lib/cretonne/meta/isa/arm64/__init__.py

@@ -7,7 +7,7 @@ ARMv8 CPUs running the Aarch64 architecture.
 
 from __future__ import absolute_import
 from . import defs
-from . import registers  # noqa
+from . import settings, registers  # noqa
 
 # Re-export the primary target ISA definition.
 ISA = defs.ISA.finish()

lib/cretonne/meta/isa/arm64/settings.py

@@ -0,0 +1,11 @@
+"""
+ARM64 settings.
+"""
+from __future__ import absolute_import
+from cdsl.settings import SettingGroup
+import base.settings as shared
+from .defs import ISA
+
+ISA.settings = SettingGroup('arm64', parent=shared.group)
+
+ISA.settings.close(globals())

lib/cretonne/meta/isa/intel/__init__.py

@@ -17,7 +17,7 @@ is no x87 floating point support.
 
 from __future__ import absolute_import
 from . import defs
-from . import registers  # noqa
+from . import settings, registers  # noqa
 
 # Re-export the primary target ISA definition.
 ISA = defs.ISA.finish()

lib/cretonne/meta/isa/intel/settings.py

@@ -0,0 +1,11 @@
+"""
+Intel settings.
+"""
+from __future__ import absolute_import
+from cdsl.settings import SettingGroup
+import base.settings as shared
+from .defs import ISA
+
+ISA.settings = SettingGroup('intel', parent=shared.group)
+
+ISA.settings.close(globals())