Move Intel recipe_* bodies into intel/recipes.py.
Use a PUT_OP macro in the TailRecipe Python class to replace the code snippet that emits the prefixes + opcode part of the instruction encoding. Prepare for the addition of REX prefixes by giving the PUT_OP functions a third argument representing the REX prefix. For the non-REX encodings, verify that no REX bits wold be needed.
This commit is contained in:
Jakob Stoklund Olesen
@@ -1,8 +1,7 @@
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//! Emitting binary Intel machine code.
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use binemit::{CodeSink, Reloc, bad_encoding};
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use ir::{self, Function, Inst, InstructionData, MemFlags};
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use ir::immediates::{Imm64, Offset32};
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use ir::{Function, Inst, InstructionData};
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use isa::RegUnit;
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include!(concat!(env!("OUT_DIR"), "/binemit-intel.rs"));
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@@ -21,27 +20,51 @@ impl Into<Reloc> for RelocKind {
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}
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}
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// Emit single-byte opcode.
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fn put_op1<CS: CodeSink + ?Sized>(bits: u16, sink: &mut CS) {
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debug_assert_eq!(bits & 0x0f00, 0, "Invalid encoding bits for Op1*");
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// Mandatory prefix bytes for Mp* opcodes.
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const PREFIX: [u8; 3] = [0x66, 0xf3, 0xf2];
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// A REX prefix with no bits set: 0b0100WRXB.
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const BASE_REX: u8 = 0b0100_0000;
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// Create a single-register REX prefix, setting the B bit to bit 3 of the register.
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// This is used for instructions that encode a register in the low 3 bits of the opcode and for
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// instructions that use the ModR/M `reg` field for something else.
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fn rex1(reg_b: RegUnit) -> u8 {
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let b = ((reg_b >> 3) & 1) as u8;
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BASE_REX | b
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}
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// Create a dual-register REX prefix, setting:
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//
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// REX.B = bit 3 of r/m register.
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// REX.R = bit 3 of reg register.
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fn rex2(rm: RegUnit, reg: RegUnit) -> u8 {
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let b = ((rm >> 3) & 1) as u8;
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let r = ((reg >> 3) & 1) as u8;
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BASE_REX | b | (r << 2)
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}
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// Emit a single-byte opcode with no REX prefix.
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fn put_op1<CS: CodeSink + ?Sized>(bits: u16, rex: u8, sink: &mut CS) {
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debug_assert_eq!(bits & 0x8f00, 0, "Invalid encoding bits for Op1*");
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debug_assert_eq!(rex, BASE_REX, "Invalid registers for REX-less encoding");
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sink.put1(bits as u8);
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}
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// Emit two-byte opcode: 0F XX
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fn put_op2<CS: CodeSink + ?Sized>(bits: u16, sink: &mut CS) {
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debug_assert_eq!(bits & 0x0f00, 0x0400, "Invalid encoding bits for Op2*");
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fn put_op2<CS: CodeSink + ?Sized>(bits: u16, rex: u8, sink: &mut CS) {
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debug_assert_eq!(bits & 0x8f00, 0x0400, "Invalid encoding bits for Op2*");
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debug_assert_eq!(rex, BASE_REX, "Invalid registers for REX-less encoding");
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sink.put1(0x0f);
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sink.put1(bits as u8);
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}
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// Mandatory prefix bytes for Mp* opcodes.
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const PREFIX: [u8; 3] = [0x66, 0xf3, 0xf2];
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// Emit single-byte opcode with mandatory prefix.
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fn put_mp1<CS: CodeSink + ?Sized>(bits: u16, sink: &mut CS) {
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fn put_mp1<CS: CodeSink + ?Sized>(bits: u16, rex: u8, sink: &mut CS) {
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debug_assert_eq!(bits & 0x0c00, 0, "Invalid encoding bits for Mp1*");
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let pp = (bits >> 8) & 3;
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sink.put1(PREFIX[(pp - 1) as usize]);
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debug_assert_eq!(rex, BASE_REX, "Invalid registers for REX-less encoding");
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sink.put1(bits as u8);
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}
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@@ -100,290 +123,3 @@ fn modrm_disp32<CS: CodeSink + ?Sized>(rm: RegUnit, reg: RegUnit, sink: &mut CS)
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b |= rm;
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sink.put1(b);
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}
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fn recipe_op1rr<CS: CodeSink + ?Sized>(_func: &Function,
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_inst: Inst,
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sink: &mut CS,
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bits: u16,
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in_reg0: RegUnit,
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in_reg1: RegUnit) {
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put_op1(bits, sink);
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modrm_rr(in_reg0, in_reg1, sink);
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}
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fn recipe_op1ur<CS: CodeSink + ?Sized>(_func: &Function,
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_inst: Inst,
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sink: &mut CS,
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bits: u16,
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in_reg0: RegUnit,
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out_reg0: RegUnit) {
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put_op1(bits, sink);
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modrm_rr(out_reg0, in_reg0, sink);
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}
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fn recipe_op1rc<CS: CodeSink + ?Sized>(_func: &Function,
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_inst: Inst,
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sink: &mut CS,
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bits: u16,
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in_reg0: RegUnit) {
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put_op1(bits, sink);
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modrm_r_bits(in_reg0, bits, sink);
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}
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fn recipe_op1rib<CS: CodeSink + ?Sized>(_func: &Function,
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_inst: Inst,
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sink: &mut CS,
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bits: u16,
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in_reg0: RegUnit,
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imm: Imm64) {
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put_op1(bits, sink);
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modrm_r_bits(in_reg0, bits, sink);
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let imm: i64 = imm.into();
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sink.put1(imm as u8);
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}
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fn recipe_op1rid<CS: CodeSink + ?Sized>(_func: &Function,
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_inst: Inst,
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sink: &mut CS,
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bits: u16,
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in_reg0: RegUnit,
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imm: Imm64) {
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put_op1(bits, sink);
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modrm_r_bits(in_reg0, bits, sink);
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let imm: i64 = imm.into();
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sink.put4(imm as u32);
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}
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fn recipe_op1uid<CS: CodeSink + ?Sized>(_func: &Function,
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_inst: Inst,
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sink: &mut CS,
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bits: u16,
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imm: Imm64,
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out_reg0: RegUnit) {
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// The destination register is encoded in the low bits of the opcode. No ModR/M
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put_op1(bits | (out_reg0 & 7), sink);
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let imm: i64 = imm.into();
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sink.put4(imm as u32);
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}
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// Store recipes.
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fn recipe_op1st<CS: CodeSink + ?Sized>(_func: &Function,
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_inst: Inst,
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sink: &mut CS,
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bits: u16,
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in_reg0: RegUnit,
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in_reg1: RegUnit,
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_flags: MemFlags,
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_offset: Offset32) {
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put_op1(bits, sink);
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modrm_rm(in_reg1, in_reg0, sink);
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}
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// This is just a tighter register class constraint.
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fn recipe_op1st_abcd<CS: CodeSink + ?Sized>(func: &Function,
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inst: Inst,
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sink: &mut CS,
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bits: u16,
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in_reg0: RegUnit,
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in_reg1: RegUnit,
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flags: MemFlags,
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offset: Offset32) {
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recipe_op1st(func, inst, sink, bits, in_reg0, in_reg1, flags, offset)
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}
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fn recipe_mp1st<CS: CodeSink + ?Sized>(_func: &Function,
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_inst: Inst,
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sink: &mut CS,
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bits: u16,
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in_reg0: RegUnit,
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in_reg1: RegUnit,
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_flags: MemFlags,
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_offset: Offset32) {
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put_mp1(bits, sink);
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modrm_rm(in_reg1, in_reg0, sink);
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}
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fn recipe_op1stdisp8<CS: CodeSink + ?Sized>(_func: &Function,
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_inst: Inst,
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sink: &mut CS,
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bits: u16,
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in_reg0: RegUnit,
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in_reg1: RegUnit,
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_flags: MemFlags,
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offset: Offset32) {
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put_op1(bits, sink);
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modrm_disp8(in_reg1, in_reg0, sink);
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let offset: i32 = offset.into();
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sink.put1(offset as u8);
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}
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fn recipe_op1stdisp8_abcd<CS: CodeSink + ?Sized>(func: &Function,
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inst: Inst,
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sink: &mut CS,
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bits: u16,
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in_reg0: RegUnit,
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in_reg1: RegUnit,
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flags: MemFlags,
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offset: Offset32) {
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recipe_op1stdisp8(func, inst, sink, bits, in_reg0, in_reg1, flags, offset)
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}
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fn recipe_mp1stdisp8<CS: CodeSink + ?Sized>(_func: &Function,
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_inst: Inst,
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sink: &mut CS,
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bits: u16,
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in_reg0: RegUnit,
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in_reg1: RegUnit,
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_flags: MemFlags,
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offset: Offset32) {
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put_mp1(bits, sink);
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modrm_disp8(in_reg1, in_reg0, sink);
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let offset: i32 = offset.into();
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sink.put1(offset as u8);
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}
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fn recipe_op1stdisp32<CS: CodeSink + ?Sized>(_func: &Function,
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_inst: Inst,
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sink: &mut CS,
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bits: u16,
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in_reg0: RegUnit,
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in_reg1: RegUnit,
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_flags: MemFlags,
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offset: Offset32) {
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put_op1(bits, sink);
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modrm_disp32(in_reg1, in_reg0, sink);
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let offset: i32 = offset.into();
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sink.put4(offset as u32);
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}
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fn recipe_op1stdisp32_abcd<CS: CodeSink + ?Sized>(func: &Function,
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inst: Inst,
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sink: &mut CS,
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bits: u16,
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in_reg0: RegUnit,
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in_reg1: RegUnit,
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flags: MemFlags,
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offset: Offset32) {
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recipe_op1stdisp32(func, inst, sink, bits, in_reg0, in_reg1, flags, offset)
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}
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fn recipe_mp1stdisp32<CS: CodeSink + ?Sized>(_func: &Function,
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_inst: Inst,
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sink: &mut CS,
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bits: u16,
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in_reg0: RegUnit,
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in_reg1: RegUnit,
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_flags: MemFlags,
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offset: Offset32) {
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put_mp1(bits, sink);
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modrm_disp32(in_reg1, in_reg0, sink);
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let offset: i32 = offset.into();
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sink.put4(offset as u32);
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}
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// Load recipes
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fn recipe_op1ld<CS: CodeSink + ?Sized>(_func: &Function,
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_inst: Inst,
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sink: &mut CS,
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bits: u16,
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in_reg0: RegUnit,
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_flags: MemFlags,
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_offset: Offset32,
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out_reg0: RegUnit) {
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put_op1(bits, sink);
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modrm_rm(in_reg0, out_reg0, sink);
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}
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fn recipe_op1lddisp8<CS: CodeSink + ?Sized>(_func: &Function,
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_inst: Inst,
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sink: &mut CS,
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bits: u16,
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in_reg0: RegUnit,
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_flags: MemFlags,
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offset: Offset32,
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out_reg0: RegUnit) {
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put_op1(bits, sink);
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modrm_disp8(in_reg0, out_reg0, sink);
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let offset: i32 = offset.into();
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sink.put1(offset as u8);
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}
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fn recipe_op1lddisp32<CS: CodeSink + ?Sized>(_func: &Function,
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_inst: Inst,
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sink: &mut CS,
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bits: u16,
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in_reg0: RegUnit,
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_flags: MemFlags,
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offset: Offset32,
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out_reg0: RegUnit) {
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put_op1(bits, sink);
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modrm_disp32(in_reg0, out_reg0, sink);
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let offset: i32 = offset.into();
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sink.put4(offset as u32);
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}
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fn recipe_op2ld<CS: CodeSink + ?Sized>(_func: &Function,
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_inst: Inst,
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sink: &mut CS,
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bits: u16,
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in_reg0: RegUnit,
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_flags: MemFlags,
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_offset: Offset32,
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out_reg0: RegUnit) {
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put_op2(bits, sink);
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modrm_rm(in_reg0, out_reg0, sink);
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}
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fn recipe_op2lddisp8<CS: CodeSink + ?Sized>(_func: &Function,
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_inst: Inst,
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sink: &mut CS,
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bits: u16,
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in_reg0: RegUnit,
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_flags: MemFlags,
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offset: Offset32,
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out_reg0: RegUnit) {
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put_op2(bits, sink);
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modrm_disp8(in_reg0, out_reg0, sink);
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let offset: i32 = offset.into();
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sink.put1(offset as u8);
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}
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fn recipe_op2lddisp32<CS: CodeSink + ?Sized>(_func: &Function,
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_inst: Inst,
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sink: &mut CS,
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bits: u16,
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in_reg0: RegUnit,
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_flags: MemFlags,
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offset: Offset32,
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out_reg0: RegUnit) {
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put_op2(bits, sink);
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modrm_disp32(in_reg0, out_reg0, sink);
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let offset: i32 = offset.into();
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sink.put4(offset as u32);
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}
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fn recipe_op1call_id<CS: CodeSink + ?Sized>(_func: &Function,
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_inst: Inst,
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sink: &mut CS,
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bits: u16,
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func_ref: ir::FuncRef) {
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put_op1(bits, sink);
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sink.reloc_func(RelocKind::PCRel4.into(), func_ref);
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sink.put4(0);
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}
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fn recipe_op1call_r<CS: CodeSink + ?Sized>(_func: &Function,
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_inst: Inst,
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sink: &mut CS,
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bits: u16,
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in_reg0: RegUnit,
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_sig_ref: ir::SigRef) {
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put_op1(bits, sink);
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modrm_r_bits(in_reg0, bits, sink);
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}
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fn recipe_op1ret<CS: CodeSink + ?Sized>(_func: &Function, _inst: Inst, sink: &mut CS, bits: u16) {
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put_op1(bits, sink);
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}
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Reference in New Issue
Block a user