ISLE: Resolve overlap in prelude.isle and x64/inst.isle (#4941)
Resolve overlap in the ISLE prelude and the x64 inst module by introducing new types that allow better sharing of extractor resuls, or falling back on priorities.
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@@ -7,7 +7,7 @@ use crate::{
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ir::AtomicRmwOp,
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machinst::{InputSourceInst, Reg, Writable},
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};
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use generated_code::{Context, MInst};
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use generated_code::{Context, MInst, RegisterClass};
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// Types that the generated ISLE code uses via `use super::*`.
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use super::{is_int_or_ref_ty, is_mergeable_load, lower_to_amode};
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@@ -546,27 +546,14 @@ impl Context for IsleContext<'_, '_, MInst, Flags, IsaFlags, 6> {
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Imm8Gpr::new(Imm8Reg::Imm8 { imm }).unwrap()
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}
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fn is_gpr_type(&mut self, ty: Type) -> Option<Type> {
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#[inline]
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fn type_register_class(&mut self, ty: Type) -> Option<RegisterClass> {
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if is_int_or_ref_ty(ty) || ty == I128 || ty == B128 {
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Some(ty)
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} else {
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None
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}
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}
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#[inline]
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fn is_xmm_type(&mut self, ty: Type) -> Option<Type> {
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if ty == F32 || ty == F64 || (ty.is_vector() && ty.bits() == 128) {
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Some(ty)
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} else {
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None
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}
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}
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#[inline]
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fn is_single_register_type(&mut self, ty: Type) -> Option<Type> {
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if ty != I128 {
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Some(ty)
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Some(RegisterClass::Gpr {
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single_register: ty != I128,
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})
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} else if ty == F32 || ty == F64 || (ty.is_vector() && ty.bits() == 128) {
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Some(RegisterClass::Xmm)
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} else {
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None
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}
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@@ -582,15 +569,6 @@ impl Context for IsleContext<'_, '_, MInst, Flags, IsaFlags, 6> {
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}
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}
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#[inline]
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fn intcc_neq(&mut self, x: &IntCC, y: &IntCC) -> Option<IntCC> {
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if x != y {
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Some(*x)
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} else {
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None
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}
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}
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#[inline]
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fn intcc_without_eq(&mut self, x: &IntCC) -> IntCC {
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x.without_equal()
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