ISLE: Resolve overlap in prelude.isle and x64/inst.isle (#4941)

Resolve overlap in the ISLE prelude and the x64 inst module by introducing new types that allow better sharing of extractor resuls, or falling back on priorities.
This commit is contained in:
Trevor Elliott
2022-09-28 10:54:39 -07:00
committed by GitHub
parent 2ba604e406
commit faf31f6216
5 changed files with 184 additions and 182 deletions

View File

@@ -7,7 +7,7 @@ use crate::{
ir::AtomicRmwOp,
machinst::{InputSourceInst, Reg, Writable},
};
use generated_code::{Context, MInst};
use generated_code::{Context, MInst, RegisterClass};
// Types that the generated ISLE code uses via `use super::*`.
use super::{is_int_or_ref_ty, is_mergeable_load, lower_to_amode};
@@ -546,27 +546,14 @@ impl Context for IsleContext<'_, '_, MInst, Flags, IsaFlags, 6> {
Imm8Gpr::new(Imm8Reg::Imm8 { imm }).unwrap()
}
fn is_gpr_type(&mut self, ty: Type) -> Option<Type> {
#[inline]
fn type_register_class(&mut self, ty: Type) -> Option<RegisterClass> {
if is_int_or_ref_ty(ty) || ty == I128 || ty == B128 {
Some(ty)
} else {
None
}
}
#[inline]
fn is_xmm_type(&mut self, ty: Type) -> Option<Type> {
if ty == F32 || ty == F64 || (ty.is_vector() && ty.bits() == 128) {
Some(ty)
} else {
None
}
}
#[inline]
fn is_single_register_type(&mut self, ty: Type) -> Option<Type> {
if ty != I128 {
Some(ty)
Some(RegisterClass::Gpr {
single_register: ty != I128,
})
} else if ty == F32 || ty == F64 || (ty.is_vector() && ty.bits() == 128) {
Some(RegisterClass::Xmm)
} else {
None
}
@@ -582,15 +569,6 @@ impl Context for IsleContext<'_, '_, MInst, Flags, IsaFlags, 6> {
}
}
#[inline]
fn intcc_neq(&mut self, x: &IntCC, y: &IntCC) -> Option<IntCC> {
if x != y {
Some(*x)
} else {
None
}
}
#[inline]
fn intcc_without_eq(&mut self, x: &IntCC) -> IntCC {
x.without_equal()