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Assert that we only use virtual registers with moves (#5440)

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Assert that we never see real registers as arguments to move instructions in VCodeBuilder::collect_operands.

Also fix a bug in the riscv64 backend that was discovered by these assertions: the lowerings of get_stack_pointer and get_frame_pointer were using physical registers 8 and 2 directly. The solution was similar to other backends: add a move instruction specifically for moving out of physical registers, whose source operand is opaque to regalloc2.
This commit is contained in:
Trevor Elliott
2022-12-20 18:22:47 -08:00
committed by GitHub
parent a308828ba2
commit fac4a915a3
6 changed files with 71 additions and 7 deletions
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10
cranelift/codegen/src/isa/riscv64/inst/mod.rs
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@@ -431,6 +431,10 @@ fn riscv64_get_operands<F: Fn(VReg) -> VReg>(inst: &Inst, collector: &mut Operan
collector.reg_use(rm);
collector.reg_def(rd);
}
&Inst::MovFromPReg { rd, rm } => {
debug_assert!([px_reg(2), px_reg(8)].contains(&rm));
collector.reg_def(rd);
}
&Inst::Fence { .. } => {}
&Inst::FenceI => {}
&Inst::ECall => {}
@@ -1530,6 +1534,12 @@ impl Inst {
};
format!("{} {},{}", v, rd, rm)
}
&MInst::MovFromPReg { rd, rm } => {
let rd = format_reg(rd.to_reg(), allocs);
debug_assert!([px_reg(2), px_reg(8)].contains(&rm));
let rm = reg_name(Reg::from(rm));
format!("mv {},{}", rd, rm)
}
&MInst::Fence { pred, succ } => {
format!(
"fence {},{}",