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Add x86 implementation of SIMD swizzle instruction

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This commit is contained in:
Andrew Brown
2020-03-06 11:29:21 -08:00
parent 4a0f53464a
commit fa7481a681
4 changed files with 85 additions and 1 deletions
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11
cranelift/filetests/filetests/isa/x86/simd-lane-access-legalize.clif
View File

@@ -83,3 +83,14 @@ block0:
; nextln: v4 = vconst.i8x16 0x00
; nextln: v1 = x86_pshufb v3, v4
; nextln: return v1
function %swizzle() -> i8x16 {
block0:
v0 = vconst.i8x16 [0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15]
v1 = vconst.i8x16 [0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15]
v2 = swizzle.i8x16 v0, v1
; check: v3 = vconst.i8x16 0x70707070707070707070707070707070
; nextln: v4 = uadd_sat v1, v3
; nextln: v2 = x86_pshufb v0, v4
return v2
}

26
cranelift/filetests/filetests/isa/x86/simd-lane-access-run.clif
View File

@@ -165,3 +165,29 @@ block0:
return v8
}
; run
function %swizzle() -> b1 {
block0:
v0 = vconst.i8x16 [0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15]
v1 = vconst.i8x16 [15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 42]
v2 = swizzle.i8x16 v0, v1 ; reverse the lanes, with over-large index 42 using lane 0
v3 = vconst.i8x16 [15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0]
v4 = icmp eq v2, v3
v5 = vall_true v4
return v5
}
; run:
function %swizzle_with_overflow() -> b1 {
block0:
v0 = vconst.i8x16 [0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15]
v1 = vconst.i8x16 [16 250 0 0 0 0 0 0 0 0 0 0 0 0 0 0]
v2 = swizzle.i8x16 v0, v1 ; 250 should overflow but saturate so that the MSB is set (PSHUFB uses this to shuffle from lane 0)
v3 = vconst.i8x16 [0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0]
v4 = icmp eq v2, v3
v5 = vall_true v4
return v5
}
; run: