From fa6e52848c1bc5075ade56e07d3fe408b746f42f Mon Sep 17 00:00:00 2001
From: bjorn3 <bjorn3@users.noreply.github.com>
Date: Sun, 20 Jun 2021 18:52:48 +0200
Subject: [PATCH] Fix warnings

---
 cranelift/codegen/src/legalizer/mod.rs | 16 ++++------------
 1 file changed, 4 insertions(+), 12 deletions(-)

diff --git a/cranelift/codegen/src/legalizer/mod.rs b/cranelift/codegen/src/legalizer/mod.rs
index d3e5745d74..3b794a1e25 100644
--- a/cranelift/codegen/src/legalizer/mod.rs
+++ b/cranelift/codegen/src/legalizer/mod.rs
@@ -13,6 +13,7 @@
 //! The legalizer does not deal with register allocation constraints. These constraints are derived
 //! from the encoding recipes, and solved later by the register allocator.
 
+#[cfg(any(feature = "x86", feature = "riscv"))]
 use crate::bitset::BitSet;
 use crate::cursor::{Cursor, FuncCursor};
 use crate::flowgraph::ControlFlowGraph;
@@ -20,19 +21,9 @@ use crate::ir::types::{I32, I64};
 use crate::ir::{self, InstBuilder, MemFlags};
 use crate::isa::TargetIsa;
 
-#[cfg(any(
-    feature = "x86",
-    feature = "arm32",
-    feature = "arm64",
-    feature = "riscv"
-))]
+#[cfg(any(feature = "x86", feature = "riscv"))]
 use crate::predicates;
-#[cfg(any(
-    feature = "x86",
-    feature = "arm32",
-    feature = "arm64",
-    feature = "riscv"
-))]
+#[cfg(any(feature = "x86", feature = "riscv"))]
 use alloc::vec::Vec;
 
 use crate::timing;
@@ -46,6 +37,7 @@ mod libcall;
 mod split;
 mod table;
 
+#[cfg(any(feature = "x86", feature = "riscv"))]
 use self::call::expand_call;
 use self::globalvalue::expand_global_value;
 use self::heap::expand_heap_addr;