Add a work-in-progress backend for x86_64 using the new instruction selection;
Most of the work is credited to Julian Seward. Co-authored-by: Julian Seward <jseward@acm.org> Co-authored-by: Chris Fallin <cfallin@mozilla.com>
This commit is contained in:
Benjamin Bouvier
358
cranelift/codegen/src/isa/x64/lower.rs
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358
cranelift/codegen/src/isa/x64/lower.rs
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//! Lowering rules for X64.
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#![allow(dead_code)]
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#![allow(non_snake_case)]
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use regalloc::{Reg, Writable};
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use crate::ir::condcodes::IntCC;
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use crate::ir::types;
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use crate::ir::Inst as IRInst;
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use crate::ir::{InstructionData, Opcode, Type};
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use crate::machinst::lower::*;
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use crate::machinst::*;
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use crate::isa::x64::inst::args::*;
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use crate::isa::x64::inst::*;
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use crate::isa::x64::X64Backend;
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/// Context passed to all lowering functions.
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type Ctx<'a> = &'a mut dyn LowerCtx<I = Inst>;
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//=============================================================================
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// Helpers for instruction lowering.
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fn is_int_ty(ty: Type) -> bool {
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match ty {
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types::I8 | types::I16 | types::I32 | types::I64 => true,
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_ => false,
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}
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}
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fn int_ty_to_is64(ty: Type) -> bool {
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match ty {
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types::I8 | types::I16 | types::I32 => false,
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types::I64 => true,
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_ => panic!("type {} is none of I8, I16, I32 or I64", ty),
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}
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}
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fn int_ty_to_sizeB(ty: Type) -> u8 {
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match ty {
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types::I8 => 1,
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types::I16 => 2,
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types::I32 => 4,
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types::I64 => 8,
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_ => panic!("ity_to_sizeB"),
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}
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}
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fn iri_to_u64_immediate<'a>(ctx: Ctx<'a>, iri: IRInst) -> Option<u64> {
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let inst_data = ctx.data(iri);
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if inst_data.opcode() == Opcode::Null {
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Some(0)
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} else {
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match inst_data {
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&InstructionData::UnaryImm { opcode: _, imm } => {
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// Only has Into for i64; we use u64 elsewhere, so we cast.
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let imm: i64 = imm.into();
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Some(imm as u64)
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}
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_ => None,
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}
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}
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}
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fn inst_condcode(data: &InstructionData) -> IntCC {
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match data {
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&InstructionData::IntCond { cond, .. }
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| &InstructionData::BranchIcmp { cond, .. }
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| &InstructionData::IntCompare { cond, .. }
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| &InstructionData::IntCondTrap { cond, .. }
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| &InstructionData::BranchInt { cond, .. }
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| &InstructionData::IntSelect { cond, .. }
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| &InstructionData::IntCompareImm { cond, .. } => cond,
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_ => panic!("inst_condcode(x64): unhandled: {:?}", data),
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}
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}
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fn intCC_to_x64_CC(cc: IntCC) -> CC {
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match cc {
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IntCC::Equal => CC::Z,
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IntCC::NotEqual => CC::NZ,
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IntCC::SignedGreaterThanOrEqual => CC::NL,
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IntCC::SignedGreaterThan => CC::NLE,
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IntCC::SignedLessThanOrEqual => CC::LE,
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IntCC::SignedLessThan => CC::L,
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IntCC::UnsignedGreaterThanOrEqual => CC::NB,
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IntCC::UnsignedGreaterThan => CC::NBE,
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IntCC::UnsignedLessThanOrEqual => CC::BE,
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IntCC::UnsignedLessThan => CC::B,
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IntCC::Overflow => CC::O,
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IntCC::NotOverflow => CC::NO,
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}
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}
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//=============================================================================
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// Top-level instruction lowering entry point, for one instruction.
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/// Actually codegen an instruction's results into registers.
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fn lower_insn_to_regs<'a>(ctx: Ctx<'a>, iri: IRInst) {
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let op = ctx.data(iri).opcode();
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let ty = if ctx.num_outputs(iri) == 1 {
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Some(ctx.output_ty(iri, 0))
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} else {
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None
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};
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// This is all outstandingly feeble. TODO: much better!
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match op {
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Opcode::Iconst => {
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if let Some(w64) = iri_to_u64_immediate(ctx, iri) {
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// Get exactly the bit pattern in 'w64' into the dest. No
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// monkeying with sign extension etc.
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let dstIs64 = w64 > 0xFFFF_FFFF;
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let regD = ctx.output(iri, 0);
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ctx.emit(Inst::imm_r(dstIs64, w64, regD));
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} else {
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unimplemented!();
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}
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}
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Opcode::Iadd | Opcode::Isub => {
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let regD = ctx.output(iri, 0);
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let regL = ctx.input(iri, 0);
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let regR = ctx.input(iri, 1);
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let is64 = int_ty_to_is64(ty.unwrap());
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let how = if op == Opcode::Iadd {
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RMI_R_Op::Add
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} else {
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RMI_R_Op::Sub
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};
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ctx.emit(Inst::mov_r_r(true, regL, regD));
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ctx.emit(Inst::alu_rmi_r(is64, how, RMI::reg(regR), regD));
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}
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Opcode::Ishl | Opcode::Ushr | Opcode::Sshr => {
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// TODO: implement imm shift value into insn
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let tySL = ctx.input_ty(iri, 0);
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let tyD = ctx.output_ty(iri, 0); // should be the same as tySL
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let regSL = ctx.input(iri, 0);
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let regSR = ctx.input(iri, 1);
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let regD = ctx.output(iri, 0);
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if tyD == tySL && (tyD == types::I32 || tyD == types::I64) {
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let how = match op {
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Opcode::Ishl => ShiftKind::Left,
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Opcode::Ushr => ShiftKind::RightZ,
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Opcode::Sshr => ShiftKind::RightS,
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_ => unreachable!(),
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};
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let is64 = tyD == types::I64;
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let r_rcx = regs::rcx();
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let w_rcx = Writable::<Reg>::from_reg(r_rcx);
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ctx.emit(Inst::mov_r_r(true, regSL, regD));
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ctx.emit(Inst::mov_r_r(true, regSR, w_rcx));
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ctx.emit(Inst::shift_r(is64, how, None /*%cl*/, regD));
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} else {
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unimplemented!()
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}
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}
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Opcode::Uextend | Opcode::Sextend => {
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// TODO: this is all extremely lame, all because Mov{ZX,SX}_M_R
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// don't accept a register source operand. They should be changed
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// so as to have _RM_R form.
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// TODO2: if the source operand is a load, incorporate that.
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let isZX = op == Opcode::Uextend;
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let tyS = ctx.input_ty(iri, 0);
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let tyD = ctx.output_ty(iri, 0);
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let regS = ctx.input(iri, 0);
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let regD = ctx.output(iri, 0);
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ctx.emit(Inst::mov_r_r(true, regS, regD));
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match (tyS, tyD, isZX) {
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(types::I8, types::I64, false) => {
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ctx.emit(Inst::shift_r(true, ShiftKind::Left, Some(56), regD));
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ctx.emit(Inst::shift_r(true, ShiftKind::RightS, Some(56), regD));
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}
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_ => unimplemented!(),
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}
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}
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Opcode::FallthroughReturn | Opcode::Return => {
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for i in 0..ctx.num_inputs(iri) {
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let src_reg = ctx.input(iri, i);
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let retval_reg = ctx.retval(i);
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ctx.emit(Inst::mov_r_r(true, src_reg, retval_reg));
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}
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// N.B.: the Ret itself is generated by the ABI.
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}
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Opcode::IaddImm
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| Opcode::ImulImm
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| Opcode::UdivImm
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| Opcode::SdivImm
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| Opcode::UremImm
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| Opcode::SremImm
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| Opcode::IrsubImm
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| Opcode::IaddCin
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| Opcode::IaddIfcin
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| Opcode::IaddCout
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| Opcode::IaddIfcout
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| Opcode::IaddCarry
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| Opcode::IaddIfcarry
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| Opcode::IsubBin
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| Opcode::IsubIfbin
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| Opcode::IsubBout
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| Opcode::IsubIfbout
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| Opcode::IsubBorrow
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| Opcode::IsubIfborrow
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| Opcode::BandImm
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| Opcode::BorImm
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| Opcode::BxorImm
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| Opcode::RotlImm
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| Opcode::RotrImm
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| Opcode::IshlImm
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| Opcode::UshrImm
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| Opcode::SshrImm => {
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panic!("ALU+imm and ALU+carry ops should not appear here!");
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}
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Opcode::X86Udivmodx
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| Opcode::X86Sdivmodx
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| Opcode::X86Umulx
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| Opcode::X86Smulx
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| Opcode::X86Cvtt2si
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| Opcode::X86Fmin
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| Opcode::X86Fmax
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| Opcode::X86Push
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| Opcode::X86Pop
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| Opcode::X86Bsr
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| Opcode::X86Bsf
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| Opcode::X86Pshufd
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| Opcode::X86Pshufb
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| Opcode::X86Pextr
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| Opcode::X86Pinsr
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| Opcode::X86Insertps
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| Opcode::X86Movsd
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| Opcode::X86Movlhps
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| Opcode::X86Psll
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| Opcode::X86Psrl
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| Opcode::X86Psra
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| Opcode::X86Ptest
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| Opcode::X86Pmaxs
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| Opcode::X86Pmaxu
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| Opcode::X86Pmins
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| Opcode::X86Pminu => {
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panic!("x86-specific opcode in supposedly arch-neutral IR!");
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}
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_ => unimplemented!("unimplemented lowering for opcode {:?}", op),
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}
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}
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//=============================================================================
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// Lowering-backend trait implementation.
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impl LowerBackend for X64Backend {
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type MInst = Inst;
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fn lower<C: LowerCtx<I = Inst>>(&self, ctx: &mut C, ir_inst: IRInst) {
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lower_insn_to_regs(ctx, ir_inst);
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}
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fn lower_branch_group<C: LowerCtx<I = Inst>>(
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&self,
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ctx: &mut C,
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branches: &[IRInst],
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targets: &[BlockIndex],
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fallthrough: Option<BlockIndex>,
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) {
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// A block should end with at most two branches. The first may be a
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// conditional branch; a conditional branch can be followed only by an
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// unconditional branch or fallthrough. Otherwise, if only one branch,
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// it may be an unconditional branch, a fallthrough, a return, or a
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// trap. These conditions are verified by `is_ebb_basic()` during the
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// verifier pass.
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assert!(branches.len() <= 2);
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let mut unimplemented = false;
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if branches.len() == 2 {
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// Must be a conditional branch followed by an unconditional branch.
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let op0 = ctx.data(branches[0]).opcode();
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let op1 = ctx.data(branches[1]).opcode();
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println!(
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"QQQQ lowering two-branch group: opcodes are {:?} and {:?}",
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op0, op1
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);
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assert!(op1 == Opcode::Jump || op1 == Opcode::Fallthrough);
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let taken = BranchTarget::Block(targets[0]);
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let not_taken = match op1 {
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Opcode::Jump => BranchTarget::Block(targets[1]),
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Opcode::Fallthrough => BranchTarget::Block(fallthrough.unwrap()),
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_ => unreachable!(), // assert above.
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};
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match op0 {
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Opcode::Brz | Opcode::Brnz => {
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let tyS = ctx.input_ty(branches[0], 0);
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if is_int_ty(tyS) {
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let rS = ctx.input(branches[0], 0);
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let cc = match op0 {
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Opcode::Brz => CC::Z,
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Opcode::Brnz => CC::NZ,
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_ => unreachable!(),
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};
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let sizeB = int_ty_to_sizeB(tyS);
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ctx.emit(Inst::cmp_rmi_r(sizeB, RMI::imm(0), rS));
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ctx.emit(Inst::jmp_cond_symm(cc, taken, not_taken));
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} else {
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unimplemented = true;
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}
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}
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Opcode::BrIcmp => {
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let tyS = ctx.input_ty(branches[0], 0);
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if is_int_ty(tyS) {
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let rSL = ctx.input(branches[0], 0);
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let rSR = ctx.input(branches[0], 1);
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let cc = intCC_to_x64_CC(inst_condcode(ctx.data(branches[0])));
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let sizeB = int_ty_to_sizeB(tyS);
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// FIXME verify rSR vs rSL ordering
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ctx.emit(Inst::cmp_rmi_r(sizeB, RMI::reg(rSR), rSL));
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ctx.emit(Inst::jmp_cond_symm(cc, taken, not_taken));
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} else {
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unimplemented = true;
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}
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}
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// TODO: Brif/icmp, Brff/icmp, jump tables
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_ => {
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unimplemented = true;
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}
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}
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} else {
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assert!(branches.len() == 1);
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// Must be an unconditional branch or trap.
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let op = ctx.data(branches[0]).opcode();
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match op {
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Opcode::Jump => {
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ctx.emit(Inst::jmp_known(BranchTarget::Block(targets[0])));
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}
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Opcode::Fallthrough => {
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ctx.emit(Inst::jmp_known(BranchTarget::Block(targets[0])));
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}
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Opcode::Trap => {
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unimplemented = true;
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}
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_ => panic!("Unknown branch type!"),
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}
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}
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if unimplemented {
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unimplemented!("lower_branch_group(x64): can't handle: {:?}", branches);
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}
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}
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}
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