Add a work-in-progress backend for x86_64 using the new instruction selection;
Most of the work is credited to Julian Seward. Co-authored-by: Julian Seward <jseward@acm.org> Co-authored-by: Chris Fallin <cfallin@mozilla.com>
This commit is contained in:
Benjamin Bouvier
261
cranelift/codegen/src/isa/x64/inst/regs.rs
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261
cranelift/codegen/src/isa/x64/inst/regs.rs
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//! Registers, the Universe thereof, and printing.
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//!
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//! These are ordered by sequence number, as required in the Universe. The strange ordering is
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//! intended to make callee-save registers available before caller-saved ones. This is a net win
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//! provided that each function makes at least one onward call. It'll be a net loss for leaf
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//! functions, and we should change the ordering in that case, so as to make caller-save regs
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//! available first.
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//!
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//! TODO Maybe have two different universes, one for leaf functions and one for non-leaf functions?
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//! Also, they will have to be ABI dependent. Need to find a way to avoid constructing a universe
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//! for each function we compile.
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use alloc::vec::Vec;
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use std::string::String;
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use regalloc::{RealReg, RealRegUniverse, Reg, RegClass, RegClassInfo, NUM_REG_CLASSES};
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use crate::machinst::pretty_print::ShowWithRRU;
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use crate::settings;
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// Hardware encodings for a few registers.
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pub const ENC_RBX: u8 = 3;
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pub const ENC_RSP: u8 = 4;
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pub const ENC_RBP: u8 = 5;
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pub const ENC_R12: u8 = 12;
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pub const ENC_R13: u8 = 13;
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pub const ENC_R14: u8 = 14;
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pub const ENC_R15: u8 = 15;
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fn gpr(enc: u8, index: u8) -> Reg {
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Reg::new_real(RegClass::I64, enc, index)
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}
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pub(crate) fn r12() -> Reg {
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gpr(ENC_R12, 0)
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}
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pub(crate) fn r13() -> Reg {
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gpr(ENC_R13, 1)
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}
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pub(crate) fn r14() -> Reg {
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gpr(ENC_R14, 2)
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}
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pub(crate) fn r15() -> Reg {
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gpr(ENC_R15, 3)
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}
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pub(crate) fn rbx() -> Reg {
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gpr(ENC_RBX, 4)
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}
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pub(crate) fn rsi() -> Reg {
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gpr(6, 5)
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}
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pub(crate) fn rdi() -> Reg {
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gpr(7, 6)
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}
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pub(crate) fn rax() -> Reg {
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gpr(0, 7)
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}
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pub(crate) fn rcx() -> Reg {
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gpr(1, 8)
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}
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pub(crate) fn rdx() -> Reg {
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gpr(2, 9)
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}
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pub(crate) fn r8() -> Reg {
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gpr(8, 10)
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}
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pub(crate) fn r9() -> Reg {
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gpr(9, 11)
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}
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pub(crate) fn r10() -> Reg {
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gpr(10, 12)
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}
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pub(crate) fn r11() -> Reg {
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gpr(11, 13)
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}
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fn fpr(enc: u8, index: u8) -> Reg {
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Reg::new_real(RegClass::V128, enc, index)
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}
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fn xmm0() -> Reg {
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fpr(0, 14)
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}
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fn xmm1() -> Reg {
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fpr(1, 15)
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}
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fn xmm2() -> Reg {
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fpr(2, 16)
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}
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fn xmm3() -> Reg {
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fpr(3, 17)
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}
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fn xmm4() -> Reg {
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fpr(4, 18)
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}
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fn xmm5() -> Reg {
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fpr(5, 19)
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}
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fn xmm6() -> Reg {
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fpr(6, 20)
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}
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fn xmm7() -> Reg {
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fpr(7, 21)
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}
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fn xmm8() -> Reg {
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fpr(8, 22)
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}
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fn xmm9() -> Reg {
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fpr(9, 23)
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}
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fn xmm10() -> Reg {
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fpr(10, 24)
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}
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fn xmm11() -> Reg {
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fpr(11, 25)
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}
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fn xmm12() -> Reg {
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fpr(12, 26)
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}
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fn xmm13() -> Reg {
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fpr(13, 27)
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}
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fn xmm14() -> Reg {
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fpr(14, 28)
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}
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fn xmm15() -> Reg {
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fpr(15, 29)
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}
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pub(crate) fn rsp() -> Reg {
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gpr(ENC_RSP, 30)
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}
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pub(crate) fn rbp() -> Reg {
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gpr(ENC_RBP, 31)
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}
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/// Create the register universe for X64.
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///
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/// The ordering of registers matters, as commented in the file doc comment: assumes the
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/// calling-convention is SystemV, at the moment.
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pub(crate) fn create_reg_universe_systemv(_flags: &settings::Flags) -> RealRegUniverse {
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let mut regs = Vec::<(RealReg, String)>::new();
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let mut allocable_by_class = [None; NUM_REG_CLASSES];
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// Integer regs.
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let mut base = regs.len();
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// Callee-saved, in the SystemV x86_64 ABI.
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regs.push((r12().to_real_reg(), "%r12".into()));
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regs.push((r13().to_real_reg(), "%r13".into()));
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regs.push((r14().to_real_reg(), "%r14".into()));
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regs.push((r15().to_real_reg(), "%r15".into()));
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regs.push((rbx().to_real_reg(), "%rbx".into()));
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// Caller-saved, in the SystemV x86_64 ABI.
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regs.push((rsi().to_real_reg(), "%rsi".into()));
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regs.push((rdi().to_real_reg(), "%rdi".into()));
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regs.push((rax().to_real_reg(), "%rax".into()));
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regs.push((rcx().to_real_reg(), "%rcx".into()));
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regs.push((rdx().to_real_reg(), "%rdx".into()));
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regs.push((r8().to_real_reg(), "%r8".into()));
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regs.push((r9().to_real_reg(), "%r9".into()));
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regs.push((r10().to_real_reg(), "%r10".into()));
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regs.push((r11().to_real_reg(), "%r11".into()));
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allocable_by_class[RegClass::I64.rc_to_usize()] = Some(RegClassInfo {
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first: base,
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last: regs.len() - 1,
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suggested_scratch: Some(r12().get_index()),
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});
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// XMM registers
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base = regs.len();
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regs.push((xmm0().to_real_reg(), "%xmm0".into()));
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regs.push((xmm1().to_real_reg(), "%xmm1".into()));
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regs.push((xmm2().to_real_reg(), "%xmm2".into()));
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regs.push((xmm3().to_real_reg(), "%xmm3".into()));
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regs.push((xmm4().to_real_reg(), "%xmm4".into()));
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regs.push((xmm5().to_real_reg(), "%xmm5".into()));
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regs.push((xmm6().to_real_reg(), "%xmm6".into()));
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regs.push((xmm7().to_real_reg(), "%xmm7".into()));
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regs.push((xmm8().to_real_reg(), "%xmm8".into()));
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regs.push((xmm9().to_real_reg(), "%xmm9".into()));
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regs.push((xmm10().to_real_reg(), "%xmm10".into()));
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regs.push((xmm11().to_real_reg(), "%xmm11".into()));
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regs.push((xmm12().to_real_reg(), "%xmm12".into()));
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regs.push((xmm13().to_real_reg(), "%xmm13".into()));
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regs.push((xmm14().to_real_reg(), "%xmm14".into()));
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regs.push((xmm15().to_real_reg(), "%xmm15".into()));
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allocable_by_class[RegClass::V128.rc_to_usize()] = Some(RegClassInfo {
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first: base,
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last: regs.len() - 1,
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suggested_scratch: Some(xmm15().get_index()),
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});
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// Other regs, not available to the allocator.
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let allocable = regs.len();
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regs.push((rsp().to_real_reg(), "%rsp".into()));
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regs.push((rbp().to_real_reg(), "%rbp".into()));
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RealRegUniverse {
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regs,
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allocable,
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allocable_by_class,
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}
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}
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/// If `ireg` denotes an I64-classed reg, make a best-effort attempt to show its name at some
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/// smaller size (4, 2 or 1 bytes).
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pub fn show_ireg_sized(reg: Reg, mb_rru: Option<&RealRegUniverse>, size: u8) -> String {
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let mut s = reg.show_rru(mb_rru);
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if reg.get_class() != RegClass::I64 || size == 8 {
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// We can't do any better.
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return s;
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}
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if reg.is_real() {
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// Change (eg) "rax" into "eax", "ax" or "al" as appropriate. This is something one could
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// describe diplomatically as "a kludge", but it's only debug code.
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let remapper = match s.as_str() {
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"%rax" => Some(["%eax", "%ax", "%al"]),
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"%rbx" => Some(["%ebx", "%bx", "%bl"]),
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"%rcx" => Some(["%ecx", "%cx", "%cl"]),
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"%rdx" => Some(["%edx", "%dx", "%dl"]),
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"%rsi" => Some(["%esi", "%si", "%sil"]),
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"%rdi" => Some(["%edi", "%di", "%dil"]),
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"%rbp" => Some(["%ebp", "%bp", "%bpl"]),
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"%rsp" => Some(["%esp", "%sp", "%spl"]),
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"%r8" => Some(["%r8d", "%r8w", "%r8b"]),
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"%r9" => Some(["%r9d", "%r9w", "%r9b"]),
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"%r10" => Some(["%r10d", "%r10w", "%r10b"]),
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"%r11" => Some(["%r11d", "%r11w", "%r11b"]),
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"%r12" => Some(["%r12d", "%r12w", "%r12b"]),
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"%r13" => Some(["%r13d", "%r13w", "%r13b"]),
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"%r14" => Some(["%r14d", "%r14w", "%r14b"]),
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"%r15" => Some(["%r15d", "%r15w", "%r15b"]),
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_ => None,
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};
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if let Some(smaller_names) = remapper {
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match size {
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4 => s = smaller_names[0].into(),
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2 => s = smaller_names[1].into(),
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1 => s = smaller_names[2].into(),
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_ => panic!("show_ireg_sized: real"),
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}
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}
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} else {
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// Add a "l", "w" or "b" suffix to RegClass::I64 vregs used at narrower widths.
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let suffix = match size {
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4 => "l",
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2 => "w",
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1 => "b",
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_ => panic!("show_ireg_sized: virtual"),
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};
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s = s + suffix;
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}
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s
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}
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