Add a work-in-progress backend for x86_64 using the new instruction selection;
Most of the work is credited to Julian Seward. Co-authored-by: Julian Seward <jseward@acm.org> Co-authored-by: Chris Fallin <cfallin@mozilla.com>
This commit is contained in:
Benjamin Bouvier
956
cranelift/codegen/src/isa/x64/inst/mod.rs
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956
cranelift/codegen/src/isa/x64/inst/mod.rs
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@@ -0,0 +1,956 @@
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//! This module defines x86_64-specific machine instruction types.
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#![allow(dead_code)]
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#![allow(non_snake_case)]
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#![allow(non_camel_case_types)]
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use std::fmt;
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use std::string::{String, ToString};
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use regalloc::RegUsageCollector;
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use regalloc::Set;
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use regalloc::{RealRegUniverse, Reg, RegClass, RegUsageMapper, SpillSlot, VirtualReg, Writable};
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use crate::binemit::CodeOffset;
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use crate::ir::types::{B1, B128, B16, B32, B64, B8, F32, F64, I128, I16, I32, I64, I8};
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use crate::ir::ExternalName;
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use crate::ir::Type;
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use crate::machinst::*;
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use crate::{settings, CodegenError, CodegenResult};
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pub mod args;
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mod emit;
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#[cfg(test)]
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mod emit_tests;
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pub mod regs;
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use args::*;
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use regs::{create_reg_universe_systemv, show_ireg_sized};
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//=============================================================================
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// Instructions (top level): definition
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// Don't build these directly. Instead use the Inst:: functions to create them.
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/// Instructions. Destinations are on the RIGHT (a la AT&T syntax).
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#[derive(Clone)]
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pub(crate) enum Inst {
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/// nops of various sizes, including zero
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Nop { len: u8 },
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/// (add sub and or xor mul adc? sbb?) (32 64) (reg addr imm) reg
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Alu_RMI_R {
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is_64: bool,
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op: RMI_R_Op,
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src: RMI,
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dst: Writable<Reg>,
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},
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/// (imm32 imm64) reg.
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/// Either: movl $imm32, %reg32 or movabsq $imm64, %reg32
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Imm_R {
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dst_is_64: bool,
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simm64: u64,
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dst: Writable<Reg>,
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},
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/// mov (64 32) reg reg
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Mov_R_R {
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is_64: bool,
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src: Reg,
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dst: Writable<Reg>,
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},
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/// movz (bl bq wl wq lq) addr reg (good for all ZX loads except 64->64).
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/// Note that the lq variant doesn't really exist since the default
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/// zero-extend rule makes it unnecessary. For that case we emit the
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/// equivalent "movl AM, reg32".
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MovZX_M_R {
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extMode: ExtMode,
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addr: Addr,
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dst: Writable<Reg>,
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},
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/// A plain 64-bit integer load, since MovZX_M_R can't represent that
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Mov64_M_R { addr: Addr, dst: Writable<Reg> },
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/// movs (bl bq wl wq lq) addr reg (good for all SX loads)
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MovSX_M_R {
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extMode: ExtMode,
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addr: Addr,
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dst: Writable<Reg>,
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},
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/// mov (b w l q) reg addr (good for all integer stores)
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Mov_R_M {
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size: u8, // 1, 2, 4 or 8
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src: Reg,
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addr: Addr,
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},
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/// (shl shr sar) (l q) imm reg
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Shift_R {
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is_64: bool,
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kind: ShiftKind,
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/// shift count: Some(0 .. #bits-in-type - 1), or None to mean "%cl".
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num_bits: Option<u8>,
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dst: Writable<Reg>,
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},
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/// cmp (b w l q) (reg addr imm) reg
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Cmp_RMI_R {
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size: u8, // 1, 2, 4 or 8
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src: RMI,
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dst: Reg,
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},
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/// pushq (reg addr imm)
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Push64 { src: RMI },
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/// popq reg
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Pop64 { dst: Writable<Reg> },
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/// call simm32
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CallKnown {
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dest: ExternalName,
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uses: Set<Reg>,
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defs: Set<Writable<Reg>>,
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},
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/// callq (reg mem)
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CallUnknown {
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dest: RM,
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//uses: Set<Reg>,
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//defs: Set<Writable<Reg>>,
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},
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// ---- branches (exactly one must appear at end of BB) ----
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/// ret
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Ret,
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/// A placeholder instruction, generating no code, meaning that a function epilogue must be
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/// inserted there.
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EpiloguePlaceholder,
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/// jmp simm32
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JmpKnown { dest: BranchTarget },
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/// jcond cond target target
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// Symmetrical two-way conditional branch.
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// Should never reach the emitter.
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JmpCondSymm {
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cc: CC,
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taken: BranchTarget,
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not_taken: BranchTarget,
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},
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/// Lowered conditional branch: contains the original instruction, and a
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/// flag indicating whether to invert the taken-condition or not. Only one
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/// BranchTarget is retained, and the other is implicitly the next
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/// instruction, given the final basic-block layout.
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JmpCond {
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cc: CC,
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//inverted: bool, is this needed?
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target: BranchTarget,
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},
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/// As for `CondBrLowered`, but represents a condbr/uncond-br sequence (two
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/// actual machine instructions). Needed when the final block layout implies
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/// that neither arm of a conditional branch targets the fallthrough block.
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// Should never reach the emitter
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JmpCondCompound {
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cc: CC,
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taken: BranchTarget,
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not_taken: BranchTarget,
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},
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/// jmpq (reg mem)
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JmpUnknown { target: RM },
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}
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// Handy constructors for Insts.
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// For various sizes, will some number of lowest bits sign extend to be the
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// same as the whole value?
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pub(crate) fn low32willSXto64(x: u64) -> bool {
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let xs = x as i64;
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xs == ((xs << 32) >> 32)
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}
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impl Inst {
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pub(crate) fn nop(len: u8) -> Self {
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debug_assert!(len <= 16);
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Self::Nop { len }
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}
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pub(crate) fn alu_rmi_r(is_64: bool, op: RMI_R_Op, src: RMI, dst: Writable<Reg>) -> Self {
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debug_assert!(dst.to_reg().get_class() == RegClass::I64);
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Self::Alu_RMI_R {
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is_64,
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op,
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src,
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dst,
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}
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}
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pub(crate) fn imm_r(dst_is_64: bool, simm64: u64, dst: Writable<Reg>) -> Inst {
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debug_assert!(dst.to_reg().get_class() == RegClass::I64);
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if !dst_is_64 {
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debug_assert!(low32willSXto64(simm64));
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}
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Inst::Imm_R {
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dst_is_64,
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simm64,
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dst,
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}
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}
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pub(crate) fn mov_r_r(is_64: bool, src: Reg, dst: Writable<Reg>) -> Inst {
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debug_assert!(src.get_class() == RegClass::I64);
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debug_assert!(dst.to_reg().get_class() == RegClass::I64);
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Inst::Mov_R_R { is_64, src, dst }
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}
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pub(crate) fn movzx_m_r(extMode: ExtMode, addr: Addr, dst: Writable<Reg>) -> Inst {
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debug_assert!(dst.to_reg().get_class() == RegClass::I64);
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Inst::MovZX_M_R { extMode, addr, dst }
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}
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pub(crate) fn mov64_m_r(addr: Addr, dst: Writable<Reg>) -> Inst {
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debug_assert!(dst.to_reg().get_class() == RegClass::I64);
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Inst::Mov64_M_R { addr, dst }
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}
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pub(crate) fn movsx_m_r(extMode: ExtMode, addr: Addr, dst: Writable<Reg>) -> Inst {
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debug_assert!(dst.to_reg().get_class() == RegClass::I64);
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Inst::MovSX_M_R { extMode, addr, dst }
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}
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pub(crate) fn mov_r_m(
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size: u8, // 1, 2, 4 or 8
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src: Reg,
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addr: Addr,
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) -> Inst {
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debug_assert!(size == 8 || size == 4 || size == 2 || size == 1);
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debug_assert!(src.get_class() == RegClass::I64);
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Inst::Mov_R_M { size, src, addr }
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}
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pub(crate) fn shift_r(
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is_64: bool,
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kind: ShiftKind,
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num_bits: Option<u8>,
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dst: Writable<Reg>,
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) -> Inst {
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debug_assert!(if let Some(num_bits) = num_bits {
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num_bits < if is_64 { 64 } else { 32 }
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} else {
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true
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});
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debug_assert!(dst.to_reg().get_class() == RegClass::I64);
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Inst::Shift_R {
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is_64,
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kind,
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num_bits,
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dst,
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}
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}
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pub(crate) fn cmp_rmi_r(
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size: u8, // 1, 2, 4 or 8
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src: RMI,
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dst: Reg,
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) -> Inst {
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debug_assert!(size == 8 || size == 4 || size == 2 || size == 1);
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debug_assert!(dst.get_class() == RegClass::I64);
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Inst::Cmp_RMI_R { size, src, dst }
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}
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pub(crate) fn push64(src: RMI) -> Inst {
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Inst::Push64 { src }
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}
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pub(crate) fn pop64(dst: Writable<Reg>) -> Inst {
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Inst::Pop64 { dst }
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}
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pub(crate) fn call_unknown(dest: RM) -> Inst {
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Inst::CallUnknown { dest }
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}
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pub(crate) fn ret() -> Inst {
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Inst::Ret
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}
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pub(crate) fn epilogue_placeholder() -> Inst {
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Inst::EpiloguePlaceholder
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}
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pub(crate) fn jmp_known(dest: BranchTarget) -> Inst {
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Inst::JmpKnown { dest }
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}
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pub(crate) fn jmp_cond_symm(cc: CC, taken: BranchTarget, not_taken: BranchTarget) -> Inst {
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Inst::JmpCondSymm {
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cc,
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taken,
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not_taken,
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}
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}
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pub(crate) fn jmp_cond(cc: CC, target: BranchTarget) -> Inst {
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Inst::JmpCond { cc, target }
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}
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pub(crate) fn jmp_cond_compound(cc: CC, taken: BranchTarget, not_taken: BranchTarget) -> Inst {
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Inst::JmpCondCompound {
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cc,
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taken,
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not_taken,
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}
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}
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pub(crate) fn jmp_unknown(target: RM) -> Inst {
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Inst::JmpUnknown { target }
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}
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}
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//=============================================================================
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// Instructions: printing
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impl ShowWithRRU for Inst {
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fn show_rru(&self, mb_rru: Option<&RealRegUniverse>) -> String {
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fn ljustify(s: String) -> String {
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let w = 7;
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if s.len() >= w {
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s
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} else {
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let need = usize::min(w, w - s.len());
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s + &format!("{nil: <width$}", nil = "", width = need)
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}
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}
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fn ljustify2(s1: String, s2: String) -> String {
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ljustify(s1 + &s2)
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}
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fn suffixLQ(is_64: bool) -> String {
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(if is_64 { "q" } else { "l" }).to_string()
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}
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fn sizeLQ(is_64: bool) -> u8 {
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if is_64 {
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8
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} else {
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4
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}
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}
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fn suffixBWLQ(size: u8) -> String {
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match size {
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1 => "b".to_string(),
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2 => "w".to_string(),
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4 => "l".to_string(),
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8 => "q".to_string(),
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_ => panic!("Inst(x64).show.suffixBWLQ: size={}", size),
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}
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}
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match self {
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Inst::Nop { len } => format!("{} len={}", ljustify("nop".to_string()), len),
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Inst::Alu_RMI_R {
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is_64,
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op,
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src,
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dst,
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} => format!(
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"{} {}, {}",
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ljustify2(op.to_string(), suffixLQ(*is_64)),
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src.show_rru_sized(mb_rru, sizeLQ(*is_64)),
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show_ireg_sized(dst.to_reg(), mb_rru, sizeLQ(*is_64)),
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),
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Inst::Imm_R {
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dst_is_64,
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simm64,
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dst,
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} => {
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if *dst_is_64 {
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format!(
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"{} ${}, {}",
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ljustify("movabsq".to_string()),
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*simm64 as i64,
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show_ireg_sized(dst.to_reg(), mb_rru, 8)
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)
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} else {
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format!(
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"{} ${}, {}",
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ljustify("movl".to_string()),
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(*simm64 as u32) as i32,
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show_ireg_sized(dst.to_reg(), mb_rru, 4)
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)
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}
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}
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Inst::Mov_R_R { is_64, src, dst } => format!(
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"{} {}, {}",
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ljustify2("mov".to_string(), suffixLQ(*is_64)),
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show_ireg_sized(*src, mb_rru, sizeLQ(*is_64)),
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show_ireg_sized(dst.to_reg(), mb_rru, sizeLQ(*is_64))
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),
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Inst::MovZX_M_R { extMode, addr, dst } => {
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if *extMode == ExtMode::LQ {
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format!(
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"{} {}, {}",
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ljustify("movl".to_string()),
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addr.show_rru(mb_rru),
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show_ireg_sized(dst.to_reg(), mb_rru, 4)
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)
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} else {
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format!(
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"{} {}, {}",
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ljustify2("movz".to_string(), extMode.to_string()),
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addr.show_rru(mb_rru),
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show_ireg_sized(dst.to_reg(), mb_rru, extMode.dst_size())
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)
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}
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}
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Inst::Mov64_M_R { addr, dst } => format!(
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"{} {}, {}",
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ljustify("movq".to_string()),
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addr.show_rru(mb_rru),
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dst.show_rru(mb_rru)
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),
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Inst::MovSX_M_R { extMode, addr, dst } => format!(
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"{} {}, {}",
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ljustify2("movs".to_string(), extMode.to_string()),
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addr.show_rru(mb_rru),
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show_ireg_sized(dst.to_reg(), mb_rru, extMode.dst_size())
|
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),
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Inst::Mov_R_M { size, src, addr } => format!(
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"{} {}, {}",
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ljustify2("mov".to_string(), suffixBWLQ(*size)),
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show_ireg_sized(*src, mb_rru, *size),
|
||||
addr.show_rru(mb_rru)
|
||||
),
|
||||
Inst::Shift_R {
|
||||
is_64,
|
||||
kind,
|
||||
num_bits,
|
||||
dst,
|
||||
} => match num_bits {
|
||||
None => format!(
|
||||
"{} %cl, {}",
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||||
ljustify2(kind.to_string(), suffixLQ(*is_64)),
|
||||
show_ireg_sized(dst.to_reg(), mb_rru, sizeLQ(*is_64))
|
||||
),
|
||||
|
||||
Some(num_bits) => format!(
|
||||
"{} ${}, {}",
|
||||
ljustify2(kind.to_string(), suffixLQ(*is_64)),
|
||||
num_bits,
|
||||
show_ireg_sized(dst.to_reg(), mb_rru, sizeLQ(*is_64))
|
||||
),
|
||||
},
|
||||
Inst::Cmp_RMI_R { size, src, dst } => format!(
|
||||
"{} {}, {}",
|
||||
ljustify2("cmp".to_string(), suffixBWLQ(*size)),
|
||||
src.show_rru_sized(mb_rru, *size),
|
||||
show_ireg_sized(*dst, mb_rru, *size)
|
||||
),
|
||||
Inst::Push64 { src } => {
|
||||
format!("{} {}", ljustify("pushq".to_string()), src.show_rru(mb_rru))
|
||||
}
|
||||
Inst::Pop64 { dst } => {
|
||||
format!("{} {}", ljustify("popq".to_string()), dst.show_rru(mb_rru))
|
||||
}
|
||||
//Inst::CallKnown { target } => format!("{} {:?}", ljustify("call".to_string()), target),
|
||||
Inst::CallKnown { .. } => "**CallKnown**".to_string(),
|
||||
Inst::CallUnknown { dest } => format!(
|
||||
"{} *{}",
|
||||
ljustify("call".to_string()),
|
||||
dest.show_rru(mb_rru)
|
||||
),
|
||||
Inst::Ret => "ret".to_string(),
|
||||
Inst::EpiloguePlaceholder => "epilogue placeholder".to_string(),
|
||||
Inst::JmpKnown { dest } => {
|
||||
format!("{} {}", ljustify("jmp".to_string()), dest.show_rru(mb_rru))
|
||||
}
|
||||
Inst::JmpCondSymm {
|
||||
cc,
|
||||
taken,
|
||||
not_taken,
|
||||
} => format!(
|
||||
"{} taken={} not_taken={}",
|
||||
ljustify2("j".to_string(), cc.to_string()),
|
||||
taken.show_rru(mb_rru),
|
||||
not_taken.show_rru(mb_rru)
|
||||
),
|
||||
//
|
||||
Inst::JmpCond { cc, ref target } => format!(
|
||||
"{} {}",
|
||||
ljustify2("j".to_string(), cc.to_string()),
|
||||
target.show_rru(None)
|
||||
),
|
||||
//
|
||||
Inst::JmpCondCompound { .. } => "**JmpCondCompound**".to_string(),
|
||||
Inst::JmpUnknown { target } => format!(
|
||||
"{} *{}",
|
||||
ljustify("jmp".to_string()),
|
||||
target.show_rru(mb_rru)
|
||||
),
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// Temp hook for legacy printing machinery
|
||||
impl fmt::Debug for Inst {
|
||||
fn fmt(&self, fmt: &mut fmt::Formatter) -> fmt::Result {
|
||||
// Print the insn without a Universe :-(
|
||||
write!(fmt, "{}", self.show_rru(None))
|
||||
}
|
||||
}
|
||||
|
||||
fn x64_get_regs(inst: &Inst, collector: &mut RegUsageCollector) {
|
||||
// This is a bit subtle. If some register is in the modified set, then it may not be in either
|
||||
// the use or def sets. However, enforcing that directly is somewhat difficult. Instead,
|
||||
// regalloc.rs will "fix" this for us by removing the the modified set from the use and def
|
||||
// sets.
|
||||
match inst {
|
||||
// ** Nop
|
||||
Inst::Alu_RMI_R {
|
||||
is_64: _,
|
||||
op: _,
|
||||
src,
|
||||
dst,
|
||||
} => {
|
||||
src.get_regs_as_uses(collector);
|
||||
collector.add_mod(*dst);
|
||||
}
|
||||
Inst::Imm_R {
|
||||
dst_is_64: _,
|
||||
simm64: _,
|
||||
dst,
|
||||
} => {
|
||||
collector.add_def(*dst);
|
||||
}
|
||||
Inst::Mov_R_R { is_64: _, src, dst } => {
|
||||
collector.add_use(*src);
|
||||
collector.add_def(*dst);
|
||||
}
|
||||
Inst::MovZX_M_R {
|
||||
extMode: _,
|
||||
addr,
|
||||
dst,
|
||||
} => {
|
||||
addr.get_regs_as_uses(collector);
|
||||
collector.add_def(*dst);
|
||||
}
|
||||
Inst::Mov64_M_R { addr, dst } => {
|
||||
addr.get_regs_as_uses(collector);
|
||||
collector.add_def(*dst);
|
||||
}
|
||||
Inst::MovSX_M_R {
|
||||
extMode: _,
|
||||
addr,
|
||||
dst,
|
||||
} => {
|
||||
addr.get_regs_as_uses(collector);
|
||||
collector.add_def(*dst);
|
||||
}
|
||||
Inst::Mov_R_M { size: _, src, addr } => {
|
||||
collector.add_use(*src);
|
||||
addr.get_regs_as_uses(collector);
|
||||
}
|
||||
Inst::Shift_R {
|
||||
is_64: _,
|
||||
kind: _,
|
||||
num_bits,
|
||||
dst,
|
||||
} => {
|
||||
if num_bits.is_none() {
|
||||
collector.add_use(regs::rcx());
|
||||
}
|
||||
collector.add_mod(*dst);
|
||||
}
|
||||
Inst::Cmp_RMI_R { size: _, src, dst } => {
|
||||
src.get_regs_as_uses(collector);
|
||||
collector.add_use(*dst); // yes, really `add_use`
|
||||
}
|
||||
Inst::Push64 { src } => {
|
||||
src.get_regs_as_uses(collector);
|
||||
collector.add_mod(Writable::from_reg(regs::rsp()));
|
||||
}
|
||||
Inst::Pop64 { dst } => {
|
||||
collector.add_def(*dst);
|
||||
}
|
||||
Inst::CallKnown {
|
||||
dest: _,
|
||||
uses: _,
|
||||
defs: _,
|
||||
} => {
|
||||
// FIXME add arg regs (iru.used) and caller-saved regs (iru.defined)
|
||||
unimplemented!();
|
||||
}
|
||||
Inst::CallUnknown { dest } => {
|
||||
dest.get_regs_as_uses(collector);
|
||||
}
|
||||
Inst::Ret => {}
|
||||
Inst::EpiloguePlaceholder => {}
|
||||
Inst::JmpKnown { dest: _ } => {}
|
||||
Inst::JmpCondSymm {
|
||||
cc: _,
|
||||
taken: _,
|
||||
not_taken: _,
|
||||
} => {}
|
||||
//
|
||||
// ** JmpCond
|
||||
//
|
||||
// ** JmpCondCompound
|
||||
//
|
||||
//Inst::JmpUnknown { target } => {
|
||||
// target.get_regs_as_uses(collector);
|
||||
//}
|
||||
Inst::Nop { .. }
|
||||
| Inst::JmpCond { .. }
|
||||
| Inst::JmpCondCompound { .. }
|
||||
| Inst::JmpUnknown { .. } => unimplemented!("x64_get_regs inst"),
|
||||
}
|
||||
}
|
||||
|
||||
//=============================================================================
|
||||
// Instructions and subcomponents: map_regs
|
||||
|
||||
fn map_use(m: &RegUsageMapper, r: &mut Reg) {
|
||||
if r.is_virtual() {
|
||||
let new = m.get_use(r.to_virtual_reg()).unwrap().to_reg();
|
||||
*r = new;
|
||||
}
|
||||
}
|
||||
|
||||
fn map_def(m: &RegUsageMapper, r: &mut Writable<Reg>) {
|
||||
if r.to_reg().is_virtual() {
|
||||
let new = m.get_def(r.to_reg().to_virtual_reg()).unwrap().to_reg();
|
||||
*r = Writable::from_reg(new);
|
||||
}
|
||||
}
|
||||
|
||||
fn map_mod(m: &RegUsageMapper, r: &mut Writable<Reg>) {
|
||||
if r.to_reg().is_virtual() {
|
||||
let new = m.get_mod(r.to_reg().to_virtual_reg()).unwrap().to_reg();
|
||||
*r = Writable::from_reg(new);
|
||||
}
|
||||
}
|
||||
|
||||
impl Addr {
|
||||
fn map_uses(&mut self, map: &RegUsageMapper) {
|
||||
match self {
|
||||
Addr::IR {
|
||||
simm32: _,
|
||||
ref mut base,
|
||||
} => map_use(map, base),
|
||||
Addr::IRRS {
|
||||
simm32: _,
|
||||
ref mut base,
|
||||
ref mut index,
|
||||
shift: _,
|
||||
} => {
|
||||
map_use(map, base);
|
||||
map_use(map, index);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
impl RMI {
|
||||
fn map_uses(&mut self, map: &RegUsageMapper) {
|
||||
match self {
|
||||
RMI::R { ref mut reg } => map_use(map, reg),
|
||||
RMI::M { ref mut addr } => addr.map_uses(map),
|
||||
RMI::I { simm32: _ } => {}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
impl RM {
|
||||
fn map_uses(&mut self, map: &RegUsageMapper) {
|
||||
match self {
|
||||
RM::R { ref mut reg } => map_use(map, reg),
|
||||
RM::M { ref mut addr } => addr.map_uses(map),
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
fn x64_map_regs(inst: &mut Inst, mapper: &RegUsageMapper) {
|
||||
// Note this must be carefully synchronized with x64_get_regs.
|
||||
match inst {
|
||||
// ** Nop
|
||||
Inst::Alu_RMI_R {
|
||||
is_64: _,
|
||||
op: _,
|
||||
ref mut src,
|
||||
ref mut dst,
|
||||
} => {
|
||||
src.map_uses(mapper);
|
||||
map_mod(mapper, dst);
|
||||
}
|
||||
Inst::Imm_R {
|
||||
dst_is_64: _,
|
||||
simm64: _,
|
||||
ref mut dst,
|
||||
} => map_def(mapper, dst),
|
||||
Inst::Mov_R_R {
|
||||
is_64: _,
|
||||
ref mut src,
|
||||
ref mut dst,
|
||||
} => {
|
||||
map_use(mapper, src);
|
||||
map_def(mapper, dst);
|
||||
}
|
||||
Inst::MovZX_M_R {
|
||||
extMode: _,
|
||||
ref mut addr,
|
||||
ref mut dst,
|
||||
} => {
|
||||
addr.map_uses(mapper);
|
||||
map_def(mapper, dst);
|
||||
}
|
||||
Inst::Mov64_M_R { addr, dst } => {
|
||||
addr.map_uses(mapper);
|
||||
map_def(mapper, dst);
|
||||
}
|
||||
Inst::MovSX_M_R {
|
||||
extMode: _,
|
||||
ref mut addr,
|
||||
ref mut dst,
|
||||
} => {
|
||||
addr.map_uses(mapper);
|
||||
map_def(mapper, dst);
|
||||
}
|
||||
Inst::Mov_R_M {
|
||||
size: _,
|
||||
ref mut src,
|
||||
ref mut addr,
|
||||
} => {
|
||||
map_use(mapper, src);
|
||||
addr.map_uses(mapper);
|
||||
}
|
||||
Inst::Shift_R {
|
||||
is_64: _,
|
||||
kind: _,
|
||||
num_bits: _,
|
||||
ref mut dst,
|
||||
} => {
|
||||
map_mod(mapper, dst);
|
||||
}
|
||||
Inst::Cmp_RMI_R {
|
||||
size: _,
|
||||
ref mut src,
|
||||
ref mut dst,
|
||||
} => {
|
||||
src.map_uses(mapper);
|
||||
map_use(mapper, dst);
|
||||
}
|
||||
Inst::Push64 { ref mut src } => src.map_uses(mapper),
|
||||
Inst::Pop64 { ref mut dst } => {
|
||||
map_def(mapper, dst);
|
||||
}
|
||||
Inst::CallKnown {
|
||||
dest: _,
|
||||
uses: _,
|
||||
defs: _,
|
||||
} => {}
|
||||
Inst::CallUnknown { dest } => dest.map_uses(mapper),
|
||||
Inst::Ret => {}
|
||||
Inst::EpiloguePlaceholder => {}
|
||||
Inst::JmpKnown { dest: _ } => {}
|
||||
Inst::JmpCondSymm {
|
||||
cc: _,
|
||||
taken: _,
|
||||
not_taken: _,
|
||||
} => {}
|
||||
//
|
||||
// ** JmpCond
|
||||
//
|
||||
// ** JmpCondCompound
|
||||
//
|
||||
//Inst::JmpUnknown { target } => {
|
||||
// target.apply_map(mapper);
|
||||
//}
|
||||
Inst::Nop { .. }
|
||||
| Inst::JmpCond { .. }
|
||||
| Inst::JmpCondCompound { .. }
|
||||
| Inst::JmpUnknown { .. } => unimplemented!("x64_map_regs opcode"),
|
||||
}
|
||||
}
|
||||
|
||||
//=============================================================================
|
||||
// Instructions: misc functions and external interface
|
||||
|
||||
impl MachInst for Inst {
|
||||
fn get_regs(&self, collector: &mut RegUsageCollector) {
|
||||
x64_get_regs(&self, collector)
|
||||
}
|
||||
|
||||
fn map_regs(&mut self, mapper: &RegUsageMapper) {
|
||||
x64_map_regs(self, mapper);
|
||||
}
|
||||
|
||||
fn is_move(&self) -> Option<(Writable<Reg>, Reg)> {
|
||||
// Note (carefully!) that a 32-bit mov *isn't* a no-op since it zeroes
|
||||
// out the upper 32 bits of the destination. For example, we could
|
||||
// conceivably use `movl %reg, %reg` to zero out the top 32 bits of
|
||||
// %reg.
|
||||
match self {
|
||||
Self::Mov_R_R { is_64, src, dst } if *is_64 => Some((*dst, *src)),
|
||||
_ => None,
|
||||
}
|
||||
}
|
||||
|
||||
fn is_epilogue_placeholder(&self) -> bool {
|
||||
if let Self::EpiloguePlaceholder = self {
|
||||
true
|
||||
} else {
|
||||
false
|
||||
}
|
||||
}
|
||||
|
||||
fn is_term<'a>(&'a self) -> MachTerminator<'a> {
|
||||
match self {
|
||||
// Interesting cases.
|
||||
&Self::Ret | &Self::EpiloguePlaceholder => MachTerminator::Ret,
|
||||
&Self::JmpKnown { dest } => MachTerminator::Uncond(dest.as_block_index().unwrap()),
|
||||
&Self::JmpCondSymm {
|
||||
cc: _,
|
||||
taken,
|
||||
not_taken,
|
||||
} => MachTerminator::Cond(
|
||||
taken.as_block_index().unwrap(),
|
||||
not_taken.as_block_index().unwrap(),
|
||||
),
|
||||
&Self::JmpCond { .. } | &Self::JmpCondCompound { .. } => {
|
||||
panic!("is_term() called after lowering branches");
|
||||
}
|
||||
// All other cases are boring.
|
||||
_ => MachTerminator::None,
|
||||
}
|
||||
}
|
||||
|
||||
fn gen_move(dst_reg: Writable<Reg>, src_reg: Reg, _ty: Type) -> Inst {
|
||||
let rc_dst = dst_reg.to_reg().get_class();
|
||||
let rc_src = src_reg.get_class();
|
||||
// If this isn't true, we have gone way off the rails.
|
||||
debug_assert!(rc_dst == rc_src);
|
||||
match rc_dst {
|
||||
RegClass::I64 => Inst::mov_r_r(true, src_reg, dst_reg),
|
||||
_ => panic!("gen_move(x64): unhandled regclass"),
|
||||
}
|
||||
}
|
||||
|
||||
fn gen_zero_len_nop() -> Inst {
|
||||
unimplemented!()
|
||||
}
|
||||
|
||||
fn gen_nop(_preferred_size: usize) -> Inst {
|
||||
unimplemented!()
|
||||
}
|
||||
|
||||
fn maybe_direct_reload(&self, _reg: VirtualReg, _slot: SpillSlot) -> Option<Inst> {
|
||||
None
|
||||
}
|
||||
|
||||
fn rc_for_type(ty: Type) -> CodegenResult<RegClass> {
|
||||
match ty {
|
||||
I8 | I16 | I32 | I64 | B1 | B8 | B16 | B32 | B64 => Ok(RegClass::I64),
|
||||
F32 | F64 | I128 | B128 => Ok(RegClass::V128),
|
||||
_ => Err(CodegenError::Unsupported(format!(
|
||||
"Unexpected SSA-value type: {}",
|
||||
ty
|
||||
))),
|
||||
}
|
||||
}
|
||||
|
||||
fn gen_jump(blockindex: BlockIndex) -> Inst {
|
||||
Inst::jmp_known(BranchTarget::Block(blockindex))
|
||||
}
|
||||
|
||||
fn with_block_rewrites(&mut self, block_target_map: &[BlockIndex]) {
|
||||
// This is identical (modulo renaming) to the arm64 version.
|
||||
match self {
|
||||
&mut Inst::JmpKnown { ref mut dest } => {
|
||||
dest.map(block_target_map);
|
||||
}
|
||||
&mut Inst::JmpCondSymm {
|
||||
cc: _,
|
||||
ref mut taken,
|
||||
ref mut not_taken,
|
||||
} => {
|
||||
taken.map(block_target_map);
|
||||
not_taken.map(block_target_map);
|
||||
}
|
||||
&mut Inst::JmpCond { .. } | &mut Inst::JmpCondCompound { .. } => {
|
||||
panic!("with_block_rewrites called after branch lowering!");
|
||||
}
|
||||
_ => {}
|
||||
}
|
||||
}
|
||||
|
||||
fn with_fallthrough_block(&mut self, fallthrough: Option<BlockIndex>) {
|
||||
// This is identical (modulo renaming) to the arm64 version.
|
||||
match self {
|
||||
&mut Inst::JmpCondSymm {
|
||||
cc,
|
||||
taken,
|
||||
not_taken,
|
||||
} => {
|
||||
if taken.as_block_index() == fallthrough {
|
||||
*self = Inst::jmp_cond(cc.invert(), not_taken);
|
||||
} else if not_taken.as_block_index() == fallthrough {
|
||||
*self = Inst::jmp_cond(cc, taken);
|
||||
} else {
|
||||
// We need a compound sequence (condbr / uncond-br).
|
||||
*self = Inst::jmp_cond_compound(cc, taken, not_taken);
|
||||
}
|
||||
}
|
||||
&mut Inst::JmpKnown { dest } => {
|
||||
if dest.as_block_index() == fallthrough {
|
||||
*self = Inst::nop(0);
|
||||
}
|
||||
}
|
||||
_ => {}
|
||||
}
|
||||
}
|
||||
|
||||
fn with_block_offsets(&mut self, my_offset: CodeOffset, targets: &[CodeOffset]) {
|
||||
// This is identical (modulo renaming) to the arm64 version.
|
||||
match self {
|
||||
&mut Self::JmpCond {
|
||||
cc: _,
|
||||
ref mut target,
|
||||
} => {
|
||||
target.lower(targets, my_offset);
|
||||
}
|
||||
&mut Self::JmpCondCompound {
|
||||
cc: _,
|
||||
ref mut taken,
|
||||
ref mut not_taken,
|
||||
..
|
||||
} => {
|
||||
taken.lower(targets, my_offset);
|
||||
not_taken.lower(targets, my_offset);
|
||||
}
|
||||
&mut Self::JmpKnown { ref mut dest } => {
|
||||
dest.lower(targets, my_offset);
|
||||
}
|
||||
_ => {}
|
||||
}
|
||||
}
|
||||
|
||||
fn reg_universe(flags: &settings::Flags) -> RealRegUniverse {
|
||||
create_reg_universe_systemv(flags)
|
||||
}
|
||||
}
|
||||
|
||||
impl<O: MachSectionOutput> MachInstEmit<O> for Inst {
|
||||
fn emit(&self, sink: &mut O, _flags: &settings::Flags) {
|
||||
emit::emit(self, sink);
|
||||
}
|
||||
}
|
||||
Reference in New Issue
Block a user