Add support for setting presets.

Fixes #11.

Presets are groups of settings and values applied at once. This is used
as a shorthand in test files, so for example "isa intel nehalem" enables
all of the CPUID bits that the Nehalem micro-architecture provides.

lib/cretonne/src/isa/intel/settings.rs

@@ -7,3 +7,27 @@ use std::fmt;
 // `Flags` struct with an impl for all of the settings defined in
 // `lib/cretonne/meta/cretonne/settings.py`.
 include!(concat!(env!("OUT_DIR"), "/settings-intel.rs"));
+
+#[cfg(test)]
+mod tests {
+    use super::{builder, Flags};
+    use settings::{self, Configurable};
+
+    #[test]
+    fn presets() {
+        let shared = settings::Flags::new(&settings::builder());
+
+        // Nehalem has SSE4.1 but not BMI1.
+        let mut b1 = builder();
+        b1.enable("nehalem").unwrap();
+        let f1 = Flags::new(&shared, &b1);
+        assert_eq!(f1.has_sse41(), true);
+        assert_eq!(f1.has_bmi1(), false);
+
+        let mut b2 = builder();
+        b2.enable("haswell").unwrap();
+        let f2 = Flags::new(&shared, &b2);
+        assert_eq!(f2.has_sse41(), true);
+        assert_eq!(f2.has_bmi1(), true);
+    }
+}

lib/cretonne/src/isa/mod.rs

@@ -108,8 +108,8 @@ impl settings::Configurable for Builder {
         self.setup.set(name, value)
     }
 
-    fn set_bool(&mut self, name: &str, value: bool) -> settings::Result<()> {
-        self.setup.set_bool(name, value)
+    fn enable(&mut self, name: &str) -> settings::Result<()> {
+        self.setup.enable(name)
     }
 }
 

lib/cretonne/src/isa/riscv/mod.rs

@@ -114,7 +114,7 @@ mod tests {
     #[test]
     fn test_64bitenc() {
         let mut shared_builder = settings::builder();
-        shared_builder.set_bool("is_64bit", true).unwrap();
+        shared_builder.enable("is_64bit").unwrap();
         let shared_flags = settings::Flags::new(&shared_builder);
         let isa = isa::lookup("riscv").unwrap().finish(shared_flags);
 
@@ -161,7 +161,7 @@ mod tests {
     #[test]
     fn test_32bitenc() {
         let mut shared_builder = settings::builder();
-        shared_builder.set_bool("is_64bit", false).unwrap();
+        shared_builder.set("is_64bit", "false").unwrap();
         let shared_flags = settings::Flags::new(&shared_builder);
         let isa = isa::lookup("riscv").unwrap().finish(shared_flags);
 
@@ -216,13 +216,13 @@ mod tests {
     #[test]
     fn test_rv32m() {
         let mut shared_builder = settings::builder();
-        shared_builder.set_bool("is_64bit", false).unwrap();
+        shared_builder.set("is_64bit", "false").unwrap();
         let shared_flags = settings::Flags::new(&shared_builder);
 
         // Set the supports_m stting which in turn enables the use_m predicate that unlocks
         // encodings for imul.
         let mut isa_builder = isa::lookup("riscv").unwrap();
-        isa_builder.set_bool("supports_m", true).unwrap();
+        isa_builder.enable("supports_m").unwrap();
 
         let isa = isa_builder.finish(shared_flags);
 

lib/cretonne/src/isa/riscv/settings.rs

@@ -34,17 +34,17 @@ mod tests {
     fn predicates() {
         let shared = settings::Flags::new(&settings::builder());
         let mut b = builder();
-        b.set_bool("supports_f", true).unwrap();
-        b.set_bool("supports_d", true).unwrap();
+        b.enable("supports_f").unwrap();
+        b.enable("supports_d").unwrap();
         let f = Flags::new(&shared, &b);
         assert_eq!(f.full_float(), true);
 
         let mut sb = settings::builder();
-        sb.set_bool("enable_simd", false).unwrap();
+        sb.set("enable_simd", "false").unwrap();
         let shared = settings::Flags::new(&sb);
         let mut b = builder();
-        b.set_bool("supports_f", true).unwrap();
-        b.set_bool("supports_d", true).unwrap();
+        b.enable("supports_f").unwrap();
+        b.enable("supports_d").unwrap();
         let f = Flags::new(&shared, &b);
         assert_eq!(f.full_float(), false);
     }