Add a few register utilities.

2017-05-02 09:59:58 -07:00
parent aaa70a677d
commit f8a3a01f96
3 changed files with 51 additions and 1 deletions
--- a/lib/cretonne/src/isa/riscv/registers.rs
+++ b/lib/cretonne/src/isa/riscv/registers.rs
@@ -6,7 +6,7 @@ include!(concat!(env!("OUT_DIR"), "/registers-riscv.rs"));

 #[cfg(test)]
 mod tests {
-    use super::INFO;
+    use super::{INFO, GPR, FPR};
    use isa::RegUnit;

    #[test]
@@ -34,4 +34,16 @@ mod tests {
        assert_eq!(uname(63), "%f31");
        assert_eq!(uname(64), "%INVALID64");
    }
+
+    #[test]
+    fn classes() {
+        assert!(GPR.contains(GPR.unit(0)));
+        assert!(GPR.contains(GPR.unit(31)));
+        assert!(!FPR.contains(GPR.unit(0)));
+        assert!(!FPR.contains(GPR.unit(31)));
+        assert!(!GPR.contains(FPR.unit(0)));
+        assert!(!GPR.contains(FPR.unit(31)));
+        assert!(FPR.contains(FPR.unit(0)));
+        assert!(FPR.contains(FPR.unit(31)));
+    }
 }