Add a few register utilities.

lib/cretonne/src/isa/registers.rs

@@ -151,6 +151,11 @@ impl RegClassData {
         let uoffset = offset * self.width as usize;
         self.first + uoffset as RegUnit
     }
+
+    /// Does this register class contain `regunit`?
+    pub fn contains(&self, regunit: RegUnit) -> bool {
+        self.mask[(regunit / 32) as usize] & (1u32 << (regunit % 32)) != 0
+    }
 }
 
 impl fmt::Display for RegClassData {

lib/cretonne/src/isa/riscv/registers.rs

@@ -6,7 +6,7 @@ include!(concat!(env!("OUT_DIR"), "/registers-riscv.rs"));
 
 #[cfg(test)]
 mod tests {
-    use super::INFO;
+    use super::{INFO, GPR, FPR};
     use isa::RegUnit;
 
     #[test]
@@ -34,4 +34,16 @@ mod tests {
         assert_eq!(uname(63), "%f31");
         assert_eq!(uname(64), "%INVALID64");
     }
+
+    #[test]
+    fn classes() {
+        assert!(GPR.contains(GPR.unit(0)));
+        assert!(GPR.contains(GPR.unit(31)));
+        assert!(!FPR.contains(GPR.unit(0)));
+        assert!(!FPR.contains(GPR.unit(31)));
+        assert!(!GPR.contains(FPR.unit(0)));
+        assert!(!GPR.contains(FPR.unit(31)));
+        assert!(FPR.contains(FPR.unit(0)));
+        assert!(FPR.contains(FPR.unit(31)));
+    }
 }