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riscv64: Remove the gen_move2 helper (#6246)

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* Remove gen_move2 from riscv64

* Update exp files
This commit is contained in:
Trevor Elliott
2023-04-19 14:04:30 -07:00
committed by GitHub
parent 8e76ec82be
commit f89ac63766
4 changed files with 24 additions and 44 deletions
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4
cranelift/codegen/src/isa/riscv64/inst.isle
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@@ -2116,10 +2116,6 @@
(extern constructor gen_stack_addr gen_stack_addr)
;; parameter are 'source register' 'in_ty' 'out_ty'
(decl gen_move2 (Reg Type Type) Reg)
(extern constructor gen_move2 gen_move2)
;;; generate a move and reinterprete the data
;; parameter is "rs" "in_type" "out_type"
(decl gen_moves (ValueRegs Type Type) ValueRegs)

10
cranelift/codegen/src/isa/riscv64/lower.isle
View File

@@ -643,7 +643,7 @@
;;;;; Rules for `ireduce`;;;;;;;;;;;;;;;;;
(rule
(lower (has_type ty (ireduce x)))
(gen_move2 (value_regs_get x 0) ty ty))
(value_regs_get x 0))
;;;;; Rules for `fpromote`;;;;;;;;;;;;;;;;;
(rule (lower (fpromote x))
@@ -721,16 +721,16 @@
(rule
(lower (isplit x))
(let
((t1 Reg (gen_move2 (value_regs_get x 0) $I64 $I64))
(t2 Reg (gen_move2 (value_regs_get x 1) $I64 $I64)))
((t1 Reg (value_regs_get x 0))
(t2 Reg (value_regs_get x 1)))
(output_pair t1 t2)))
;;;;; Rules for `iconcat`;;;;;;;;;
(rule
(lower (has_type $I128 (iconcat x y)))
(let
((t1 Reg (gen_move2 x $I64 $I64))
(t2 Reg (gen_move2 y $I64 $I64)))
((t1 Reg x)
(t2 Reg y))
(value_regs t1 t2)))
;;;;; Rules for `smax`;;;;;;;;;

12
cranelift/codegen/src/isa/riscv64/lower/isle.rs
View File

@@ -114,18 +114,18 @@ impl generated_code::Context for IsleContext<'_, '_, MInst, Riscv64Backend> {
});
}
fn load_ra(&mut self) -> Reg {
let tmp = self.temp_writable_reg(I64);
if self.backend.flags.preserve_frame_pointers() {
let tmp = self.temp_writable_reg(I64);
self.emit(&MInst::Load {
rd: tmp,
op: LoadOP::Ld,
flags: MemFlags::trusted(),
from: AMode::FPOffset(8, I64),
});
tmp.to_reg()
} else {
self.gen_move2(link_reg(), I64, I64)
self.emit(&gen_move(tmp, I64, link_reg(), I64));
}
tmp.to_reg()
}
fn int_zero_reg(&mut self, ty: Type) -> ValueRegs {
assert!(ty.is_int(), "{:?}", ty);
@@ -380,12 +380,6 @@ impl generated_code::Context for IsleContext<'_, '_, MInst, Riscv64Backend> {
AMO::SeqCst
}
fn gen_move2(&mut self, r: Reg, ity: Type, oty: Type) -> Reg {
let tmp = self.temp_writable_reg(oty);
self.emit(&gen_move(tmp, oty, r, ity));
tmp.to_reg()
}
fn lower_br_table(&mut self, index: Reg, targets: &VecMachLabel) -> Unit {
let tmp1 = self.temp_writable_reg(I64);
let tmp2 = self.temp_writable_reg(I64);