ARM64 backend, part 2 / 11: remove old ARM64 backend.
This removes the old ARM64 backend completely, leaving only an empty `arm64` module. The tree at this state will not build with the `arm64` feature enabled, but that feature has to be enabled explicitly (it is not default). Subsequent patches will fill in the new backend.
This commit is contained in:
Chris Fallin
@@ -1,31 +0,0 @@
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//! ARM 64 ABI implementation.
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use super::registers::{FPR, GPR};
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use crate::ir;
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use crate::isa::RegClass;
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use crate::regalloc::RegisterSet;
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use crate::settings as shared_settings;
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use alloc::borrow::Cow;
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/// Legalize `sig`.
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pub fn legalize_signature(
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_sig: &mut Cow<ir::Signature>,
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_flags: &shared_settings::Flags,
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_current: bool,
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) {
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unimplemented!()
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}
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/// Get register class for a type appearing in a legalized signature.
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pub fn regclass_for_abi_type(ty: ir::Type) -> RegClass {
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if ty.is_int() {
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GPR
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} else {
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FPR
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}
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}
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/// Get the set of allocatable registers for `func`.
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pub fn allocatable_registers(_func: &ir::Function) -> RegisterSet {
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unimplemented!()
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}
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@@ -1,8 +0,0 @@
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//! Emitting binary ARM64 machine code.
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use crate::binemit::{bad_encoding, CodeSink};
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use crate::ir::{Function, Inst};
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use crate::isa::TargetIsa;
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use crate::regalloc::RegDiversions;
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include!(concat!(env!("OUT_DIR"), "/binemit-arm64.rs"));
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@@ -1,10 +0,0 @@
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//! Encoding tables for ARM64 ISA.
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use crate::ir;
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use crate::isa;
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use crate::isa::constraints::*;
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use crate::isa::enc_tables::*;
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use crate::isa::encoding::RecipeSizing;
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include!(concat!(env!("OUT_DIR"), "/encoding-arm64.rs"));
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include!(concat!(env!("OUT_DIR"), "/legalize-arm64.rs"));
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@@ -1,132 +1 @@
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//! ARM 64-bit Instruction Set Architecture.
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mod abi;
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mod binemit;
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mod enc_tables;
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mod registers;
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pub mod settings;
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use super::super::settings as shared_settings;
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#[cfg(feature = "testing_hooks")]
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use crate::binemit::CodeSink;
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use crate::binemit::{emit_function, MemoryCodeSink};
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use crate::ir;
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use crate::isa::enc_tables::{lookup_enclist, Encodings};
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use crate::isa::Builder as IsaBuilder;
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use crate::isa::{EncInfo, RegClass, RegInfo, TargetIsa};
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use crate::regalloc;
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use alloc::borrow::Cow;
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use alloc::boxed::Box;
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use core::fmt;
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use target_lexicon::Triple;
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#[allow(dead_code)]
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struct Isa {
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triple: Triple,
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shared_flags: shared_settings::Flags,
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isa_flags: settings::Flags,
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}
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/// Get an ISA builder for creating ARM64 targets.
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pub fn isa_builder(triple: Triple) -> IsaBuilder {
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IsaBuilder {
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triple,
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setup: settings::builder(),
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constructor: isa_constructor,
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}
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}
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fn isa_constructor(
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triple: Triple,
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shared_flags: shared_settings::Flags,
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builder: shared_settings::Builder,
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) -> Box<dyn TargetIsa> {
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Box::new(Isa {
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triple,
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isa_flags: settings::Flags::new(&shared_flags, builder),
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shared_flags,
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})
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}
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impl TargetIsa for Isa {
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fn name(&self) -> &'static str {
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"arm64"
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}
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fn triple(&self) -> &Triple {
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&self.triple
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}
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fn flags(&self) -> &shared_settings::Flags {
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&self.shared_flags
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}
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fn register_info(&self) -> RegInfo {
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registers::INFO.clone()
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}
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fn encoding_info(&self) -> EncInfo {
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enc_tables::INFO.clone()
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}
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fn legal_encodings<'a>(
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&'a self,
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func: &'a ir::Function,
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inst: &'a ir::InstructionData,
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ctrl_typevar: ir::Type,
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) -> Encodings<'a> {
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lookup_enclist(
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ctrl_typevar,
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inst,
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func,
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&enc_tables::LEVEL1_A64[..],
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&enc_tables::LEVEL2[..],
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&enc_tables::ENCLISTS[..],
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&enc_tables::LEGALIZE_ACTIONS[..],
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&enc_tables::RECIPE_PREDICATES[..],
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&enc_tables::INST_PREDICATES[..],
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self.isa_flags.predicate_view(),
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)
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}
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fn legalize_signature(&self, sig: &mut Cow<ir::Signature>, current: bool) {
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abi::legalize_signature(sig, &self.shared_flags, current)
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}
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fn regclass_for_abi_type(&self, ty: ir::Type) -> RegClass {
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abi::regclass_for_abi_type(ty)
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}
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fn allocatable_registers(&self, func: &ir::Function) -> regalloc::RegisterSet {
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abi::allocatable_registers(func)
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}
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#[cfg(feature = "testing_hooks")]
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fn emit_inst(
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&self,
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func: &ir::Function,
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inst: ir::Inst,
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divert: &mut regalloc::RegDiversions,
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sink: &mut dyn CodeSink,
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) {
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binemit::emit_inst(func, inst, divert, sink, self)
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}
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fn emit_function_to_memory(&self, func: &ir::Function, sink: &mut MemoryCodeSink) {
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emit_function(func, binemit::emit_inst, sink, self)
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}
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fn unsigned_add_overflow_condition(&self) -> ir::condcodes::IntCC {
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ir::condcodes::IntCC::UnsignedLessThan
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}
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fn unsigned_sub_overflow_condition(&self) -> ir::condcodes::IntCC {
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ir::condcodes::IntCC::UnsignedGreaterThanOrEqual
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}
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}
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impl fmt::Display for Isa {
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fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
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write!(f, "{}\n{}", self.shared_flags, self.isa_flags)
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}
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}
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// Empty.
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@@ -1,39 +0,0 @@
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//! ARM64 register descriptions.
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use crate::isa::registers::{RegBank, RegClass, RegClassData, RegInfo, RegUnit};
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include!(concat!(env!("OUT_DIR"), "/registers-arm64.rs"));
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#[cfg(test)]
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mod tests {
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use super::INFO;
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use crate::isa::RegUnit;
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use alloc::string::{String, ToString};
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#[test]
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fn unit_encodings() {
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assert_eq!(INFO.parse_regunit("x0"), Some(0));
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assert_eq!(INFO.parse_regunit("x31"), Some(31));
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assert_eq!(INFO.parse_regunit("v0"), Some(32));
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assert_eq!(INFO.parse_regunit("v31"), Some(63));
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assert_eq!(INFO.parse_regunit("x32"), None);
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assert_eq!(INFO.parse_regunit("v32"), None);
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}
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#[test]
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fn unit_names() {
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fn uname(ru: RegUnit) -> String {
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INFO.display_regunit(ru).to_string()
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}
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assert_eq!(uname(0), "%x0");
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assert_eq!(uname(1), "%x1");
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assert_eq!(uname(31), "%x31");
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assert_eq!(uname(32), "%v0");
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assert_eq!(uname(33), "%v1");
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assert_eq!(uname(63), "%v31");
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assert_eq!(uname(64), "%nzcv");
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assert_eq!(uname(65), "%INVALID65");
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}
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}
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@@ -1,9 +0,0 @@
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//! ARM64 Settings.
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use crate::settings::{self, detail, Builder};
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use core::fmt;
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// Include code generated by `cranelift-codegen/meta/src/gen_settings.rs`. This file contains a
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// public `Flags` struct with an impl for all of the settings defined in
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// `cranelift-codegen/meta/src/isa/arm64/mod.rs`.
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include!(concat!(env!("OUT_DIR"), "/settings-arm64.rs"));
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@@ -116,7 +116,6 @@ pub fn lookup(triple: Triple) -> Result<Builder, LookupError> {
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isa_builder!(x86, "x86", triple)
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}
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Architecture::Arm { .. } => isa_builder!(arm32, "arm32", triple),
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Architecture::Aarch64 { .. } => isa_builder!(arm64, "arm64", triple),
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_ => Err(LookupError::Unsupported),
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}
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}
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