riscv64: Improve signed and zero extend codegen (#5844)

* riscv64: Remove unused code

* riscv64: Group extend rules

* riscv64: Remove more unused rules

* riscv64: Cleanup existing extension rules

* riscv64: Move the existing Extend rules to ISLE

* riscv64: Use `sext.w` when extending

* riscv64: Remove duplicate extend tests

* riscv64: Use `zbb` instructions when extending values

* riscv64: Use `zbkb` extensions when zero extending

* riscv64: Enable additional tests for extend i128

* riscv64: Fix formatting for `Inst::Extend`

* riscv64: Reverse register for pack

* riscv64: Misc Cleanups

* riscv64: Cleanup extend rules

cranelift/codegen/src/isa/riscv64/inst.isle

@@ -569,6 +569,11 @@
   (Clmul)
   (Clmulh)
   (Clmulr)
+
+  ;; Zbkb: Bit-manipulation for Cryptography
+  (Pack)
+  (Packw)
+  (Packh)
 ))
 
 
@@ -858,22 +863,6 @@
             (_ Unit (emit (MInst.AluRRImm12 op dst src (imm12_zero)))))
         dst))
 
-;; extend int if need.
-(decl ext_int_if_need (bool ValueRegs Type) ValueRegs)
-;;; for I8, I16, and I32 ...
-(rule -1
-  (ext_int_if_need signed val ty)
-  (gen_extend val signed (ty_bits ty) 64))
-;;; otherwise this is a I64 or I128
-;;; no need to extend.
-(rule
-  (ext_int_if_need _ r  $I64)
-  r)
-(rule
-  (ext_int_if_need _ r  $I128)
-  r)
-
-
 ;; Helper for get negative of Imm12
 (decl neg_imm12 (Imm12) Imm12)
 (extern constructor neg_imm12 neg_imm12)
@@ -1032,49 +1021,115 @@
       (result Reg (alu_add high low)))
     (value_regs result (load_u64_constant 0))))
   
-(decl gen_extend (Reg bool u8 u8) Reg)
-(rule
-  (gen_extend r is_signed from_bits to_bits)
-  (let
-    ((tmp WritableReg (temp_writable_reg $I16))
-      (_ Unit (emit (MInst.Extend tmp r is_signed from_bits to_bits))))
-    tmp))
-
-;; val is_signed from_bits to_bits
-(decl lower_extend (Reg bool u8 u8) ValueRegs)
-(rule -1
-  (lower_extend r is_signed from_bits to_bits)
-  (gen_extend r is_signed from_bits to_bits))
-
-;;;; for I128 signed extend.
-(rule 1
-  (lower_extend r $true 64 128)
-  (let
-    ((tmp Reg (alu_rrr (AluOPRRR.Slt) r (zero_reg)))
-      (high Reg (gen_extend tmp $true 1 64)))
-    (value_regs (gen_move2 r $I64 $I64) high)))
-
-(rule
-  (lower_extend r $true from_bits 128)
-  (let
-    ((tmp Reg (gen_extend r $true from_bits 64))
-      (tmp2 Reg (alu_rrr (AluOPRRR.Slt) tmp (zero_reg)))
-      (high Reg (gen_extend tmp2 $true 1 64)))
-    (value_regs (gen_move2 tmp $I64 $I64) high)))
+;; Extends an integer if it is smaller than 64 bits.
+(decl ext_int_if_need (bool ValueRegs Type) ValueRegs)
+;;; For values smaller than 64 bits, we need to extend them to 64 bits
+(rule 0 (ext_int_if_need $true val (fits_in_32 (ty_int ty)))
+  (sext val ty $I64))
+(rule 0 (ext_int_if_need $false val (fits_in_32 (ty_int ty)))
+  (zext val ty $I64))
+;; If the value is larger than one machine register, we don't need to do anything
+(rule 1 (ext_int_if_need _ r $I64) r)
+(rule 2 (ext_int_if_need _ r $I128) r)
 
 
-;;;; for I128 unsigned extend.
-(rule 1
-  (lower_extend r $false 64 128)
-  (value_regs (gen_move2 r $I64 $I64) (load_u64_constant 0)))
+;; Performs a zero extension of the given value
+(decl zext (ValueRegs Type Type) ValueRegs)
+(rule (zext val from_ty to_ty) (extend val (ExtendOp.Zero) from_ty to_ty))
+
+;; Performs a signed extension of the given value
+(decl sext (ValueRegs Type Type) ValueRegs)
+(rule (sext val from_ty to_ty) (extend val (ExtendOp.Signed) from_ty to_ty))
+
+(type ExtendOp
+  (enum
+    (Zero)
+    (Signed)))
+
+;; Performs either a sign or zero extension of the given value
+(decl extend (ValueRegs ExtendOp Type Type) ValueRegs)
+
+;;; Generic Rules Extending to I64
+(decl pure extend_shift_op (ExtendOp) AluOPRRI)
+(rule (extend_shift_op (ExtendOp.Zero)) (AluOPRRI.Srli))
+(rule (extend_shift_op (ExtendOp.Signed)) (AluOPRRI.Srai))
+
+;; In the most generic case, we shift left and then shift right.
+;; The type of right shift is determined by the extend op.
+(rule 0 (extend val extend_op (fits_in_32 from_ty) (fits_in_64 to_ty))
+  (let ((val Reg (value_regs_get val 0))
+        (shift Imm12 (imm_from_bits (u64_sub 64 (ty_bits from_ty))))
+        (left Reg (alu_rr_imm12 (AluOPRRI.Slli) val shift))
+        (shift_op AluOPRRI (extend_shift_op extend_op))
+        (right Reg (alu_rr_imm12 shift_op left shift)))
+    right))
+
+;; If we are zero extending a U8 we can use a `andi` instruction.
+(rule 1 (extend val (ExtendOp.Zero) $I8 (fits_in_64 to_ty))
+  (let ((val Reg (value_regs_get val 0)))
+    (alu_rr_imm12 (AluOPRRI.Andi) val (imm12_const 255))))
+
+;; When signed extending from 32 to 64 bits we can use a
+;; `addiw val 0`. Also known as a `sext.w`
+(rule 1 (extend val (ExtendOp.Signed) $I32 $I64)
+  (let ((val Reg (value_regs_get val 0)))
+    (alu_rr_imm12 (AluOPRRI.Addiw) val (imm12_const 0))))
+
+
+;; No point in trying to use `packh` here to zero extend 8 bit values
+;; since we can just use `andi` instead which is part of the base ISA.
+
+;; If we have the `zbkb` extension `packw` can be used to zero extend 16 bit values
+(rule 1 (extend val (ExtendOp.Zero) $I16 (fits_in_64 _))
+  (if-let $true (has_zbkb))
+  (let ((val Reg (value_regs_get val 0)))
+    (alu_rrr (AluOPRRR.Packw) val (zero_reg))))
+
+;; If we have the `zbkb` extension `pack` can be used to zero extend 32 bit registers
+(rule 1 (extend val (ExtendOp.Zero) $I32 $I64)
+  (if-let $true (has_zbkb))
+  (let ((val Reg (value_regs_get val 0)))
+    (alu_rrr (AluOPRRR.Pack) val (zero_reg))))
+
+
+;; If we have the `zbb` extension we can use the dedicated `sext.b` instruction.
+(rule 1 (extend val (ExtendOp.Signed) $I8 (fits_in_64 _))
+  (if-let $true (has_zbb))
+  (let ((val Reg (value_regs_get val 0)))
+    (alu_rr_imm12 (AluOPRRI.Sextb) val (imm12_const 0))))
+
+;; If we have the `zbb` extension we can use the dedicated `sext.h` instruction.
+(rule 1 (extend val (ExtendOp.Signed) $I16 (fits_in_64 _))
+  (if-let $true (has_zbb))
+  (let ((val Reg (value_regs_get val 0)))
+    (alu_rr_imm12 (AluOPRRI.Sexth) val (imm12_const 0))))
+
+;; If we have the `zbb` extension we can use the dedicated `zext.h` instruction.
+(rule 2 (extend val (ExtendOp.Zero) $I16 (fits_in_64 _))
+  (if-let $true (has_zbb))
+  (let ((val Reg (value_regs_get val 0)))
+    (alu_rr_imm12 (AluOPRRI.Zexth) val (imm12_const 0))))
+
+;;; Signed rules extending to I128
+;; Extend the bottom part, and extract the sign bit from the bottom as the top
+(rule 2 (extend val (ExtendOp.Signed) (fits_in_64 from_ty) $I128)
+  (let ((val Reg (value_regs_get val 0))
+        (low Reg (extend val (ExtendOp.Signed) from_ty $I64))
+        (high Reg (alu_rr_imm12 (AluOPRRI.Srai) low (imm12_const 63))))
+    (value_regs low high)))
+
+;;; Unsigned rules extending to I128
+;; Extend the bottom register to I64 and then just zero out the top half.
+(rule 3 (extend val (ExtendOp.Zero) (fits_in_64 from_ty) $I128)
+  (let ((val Reg (value_regs_get val 0))
+        (low Reg (extend val (ExtendOp.Zero) from_ty $I64))
+        (high Reg (load_u64_constant 0)))
+    (value_regs low high)))
+
+;; Catch all rule for ignoring extensions of the same type.
+(rule 4 (extend val _ ty ty) val)
 
-(rule
-  (lower_extend r $false from_bits 128)
-  (value_regs (gen_extend r $false from_bits 64) (load_u64_constant 0)))
 
-;; extract the sign bit of integer.
-(decl ext_sign_bit (Type Reg) Reg)
-(extern constructor ext_sign_bit ext_sign_bit)
 
 (decl lower_b128_binary (AluOPRRR ValueRegs ValueRegs) ValueRegs)
 (rule
@@ -1795,50 +1850,6 @@
 (rule (lower_icmp cc x y ty)
   (gen_icmp cc (ext_int_if_need $false x ty) (ext_int_if_need $false y ty) ty))
 
-(decl lower_icmp_over_flow (ValueRegs ValueRegs Type) Reg)
-
-;;; for I8 I16 I32
-(rule 1
-  (lower_icmp_over_flow x y ty)
-  (let
-    ((tmp Reg (alu_sub (ext_int_if_need $true x ty) (ext_int_if_need $true y ty)))
-      (tmp2 WritableReg (temp_writable_reg $I64))
-      (_ Unit (emit (MInst.Extend tmp2 tmp $true (ty_bits ty) 64))))
-    (gen_icmp (IntCC.NotEqual) (writable_reg_to_reg tmp2) tmp $I64)))
-
-;;; $I64
-(rule 3
-  (lower_icmp_over_flow x y $I64)
-  (let
-    ((y_sign Reg (alu_rrr (AluOPRRR.Sgt) y (zero_reg)))
-       (sub_result Reg (alu_sub x y))
-       (tmp Reg (alu_rrr (AluOPRRR.Slt) sub_result x)))
-    (gen_icmp (IntCC.NotEqual) y_sign tmp $I64)))
-
-;;; $I128
-(rule 2
-  (lower_icmp_over_flow x y $I128)
-  (let
-    ( ;; x sign bit.
-      (xs Reg (alu_rr_imm12 (AluOPRRI.Srli) (value_regs_get x 1) (imm12_const 63)))
-      ;; y sign bit.
-      (ys Reg (alu_rr_imm12 (AluOPRRI.Srli) (value_regs_get y 1) (imm12_const 63)))
-      ;;
-      (sub_result ValueRegs (i128_sub x y))
-      ;; result sign bit.
-      (rs Reg (alu_rr_imm12 (AluOPRRI.Srli) (value_regs_get sub_result 1) (imm12_const 63)))
-
-      ;;; xs && !ys && !rs
-      ;;; x is positive y is negtive and result is negative.
-      ;;; must overflow
-      (tmp1 Reg (alu_and xs (alu_and (gen_bit_not ys) (gen_bit_not rs))))
-      ;;; !xs && ys && rs
-      ;;; x is negative y is positive and result is positive.
-      ;;; overflow
-      (tmp2 Reg (alu_and (gen_bit_not xs) (alu_and ys rs)))
-      ;;;tmp3
-      (tmp3 Reg (alu_rrr (AluOPRRR.Or) tmp1 tmp2)))
-    (gen_extend tmp3 $true 1 64)))
 
 (decl i128_sub (ValueRegs ValueRegs) ValueRegs)
 (rule

cranelift/codegen/src/isa/riscv64/inst/args.rs

@@ -746,6 +746,9 @@ impl AluOPRRR {
             Self::Sh3add => "sh3add",
             Self::Sh3adduw => "sh3add.uw",
             Self::Xnor => "xnor",
+            Self::Pack => "pack",
+            Self::Packw => "packw",
+            Self::Packh => "packh",
         }
     }
 
@@ -785,6 +788,7 @@ impl AluOPRRR {
             AluOPRRR::Remw => 0b110,
             AluOPRRR::Remuw => 0b111,
 
+            // Zbb
             AluOPRRR::Adduw => 0b000,
             AluOPRRR::Andn => 0b111,
             AluOPRRR::Bclr => 0b001,
@@ -810,6 +814,11 @@ impl AluOPRRR {
             AluOPRRR::Sh3add => 0b110,
             AluOPRRR::Sh3adduw => 0b110,
             AluOPRRR::Xnor => 0b100,
+
+            // Zbkb
+            AluOPRRR::Pack => 0b100,
+            AluOPRRR::Packw => 0b100,
+            AluOPRRR::Packh => 0b111,
         }
     }
 
@@ -826,11 +835,16 @@ impl AluOPRRR {
             | AluOPRRR::Srl
             | AluOPRRR::Sra
             | AluOPRRR::Or
-            | AluOPRRR::And => 0b0110011,
+            | AluOPRRR::And
+            | AluOPRRR::Pack
+            | AluOPRRR::Packh => 0b0110011,
 
-            AluOPRRR::Addw | AluOPRRR::Subw | AluOPRRR::Sllw | AluOPRRR::Srlw | AluOPRRR::Sraw => {
-                0b0111011
-            }
+            AluOPRRR::Addw
+            | AluOPRRR::Subw
+            | AluOPRRR::Sllw
+            | AluOPRRR::Srlw
+            | AluOPRRR::Sraw
+            | AluOPRRR::Packw => 0b0111011,
 
             AluOPRRR::Mul
             | AluOPRRR::Mulh
@@ -937,6 +951,11 @@ impl AluOPRRR {
             AluOPRRR::Sh3add => 0b0010000,
             AluOPRRR::Sh3adduw => 0b0010000,
             AluOPRRR::Xnor => 0b0100000,
+
+            // Zbkb
+            AluOPRRR::Pack => 0b0000100,
+            AluOPRRR::Packw => 0b0000100,
+            AluOPRRR::Packh => 0b0000100,
         }
     }
 

cranelift/codegen/src/isa/riscv64/inst/emit_tests.rs

@@ -514,6 +514,38 @@ fn test_riscv64_binemit() {
         0x400545b3,
     ));
 
+    // Zbkb
+    insns.push(TestUnit::new(
+        Inst::AluRRR {
+            alu_op: AluOPRRR::Pack,
+            rd: writable_a1(),
+            rs1: a0(),
+            rs2: zero_reg(),
+        },
+        "pack a1,a0,zero",
+        0x080545b3,
+    ));
+    insns.push(TestUnit::new(
+        Inst::AluRRR {
+            alu_op: AluOPRRR::Packw,
+            rd: writable_a1(),
+            rs1: a0(),
+            rs2: zero_reg(),
+        },
+        "packw a1,a0,zero",
+        0x080545bb,
+    ));
+    insns.push(TestUnit::new(
+        Inst::AluRRR {
+            alu_op: AluOPRRR::Packh,
+            rd: writable_a1(),
+            rs1: a0(),
+            rs2: zero_reg(),
+        },
+        "packh a1,a0,zero",
+        0x080575b3,
+    ));
+
     //
     insns.push(TestUnit::new(
         Inst::AluRRR {

cranelift/codegen/src/isa/riscv64/inst/mod.rs

@@ -845,16 +845,6 @@ impl Inst {
             x
         };
 
-        fn format_extend_op(signed: bool, from_bits: u8, _to_bits: u8) -> String {
-            let type_name = match from_bits {
-                1 => "b1",
-                8 => "b",
-                16 => "h",
-                32 => "w",
-                _ => unreachable!("from_bits:{:?}", from_bits),
-            };
-            format!("{}ext.{}", if signed { "s" } else { "u" }, type_name)
-        }
         fn format_frm(rounding_mode: Option<FRM>) -> String {
             if let Some(r) = rounding_mode {
                 format!(",{}", r.to_static_str(),)
@@ -1341,15 +1331,23 @@ impl Inst {
             } => {
                 let rs_s = format_reg(rs, allocs);
                 let rd = format_reg(rd.to_reg(), allocs);
-                // check if it is a load constant.
-                if alu_op == AluOPRRI::Addi && rs == zero_reg() {
-                    format!("li {},{}", rd, imm12.as_i16())
-                } else if alu_op == AluOPRRI::Xori && imm12.as_i16() == -1 {
-                    format!("not {},{}", rd, rs_s)
-                } else {
-                    if alu_op.option_funct12().is_some() {
+
+                // Some of these special cases are better known as
+                // their pseudo-instruction version, so prefer printing those.
+                match (alu_op, rs, imm12) {
+                    (AluOPRRI::Addi, rs, _) if rs == zero_reg() => {
+                        return format!("li {},{}", rd, imm12.as_i16());
+                    }
+                    (AluOPRRI::Addiw, _, imm12) if imm12.as_i16() == 0 => {
+                        return format!("sext.w {},{}", rd, rs_s);
+                    }
+                    (AluOPRRI::Xori, _, imm12) if imm12.as_i16() == -1 => {
+                        return format!("not {},{}", rd, rs_s);
+                    }
+                    (alu_op, _, _) if alu_op.option_funct12().is_some() => {
                         format!("{} {},{}", alu_op.op_name(), rd, rs_s)
-                    } else {
+                    }
+                    (alu_op, _, imm12) => {
                         format!("{} {},{},{}", alu_op.op_name(), rd, rs_s, imm12.as_i16())
                     }
                 }
@@ -1402,16 +1400,17 @@ impl Inst {
                 rn,
                 signed,
                 from_bits,
-                to_bits,
+                ..
             } => {
                 let rn = format_reg(rn, allocs);
-                let rm = format_reg(rd.to_reg(), allocs);
-                format!(
-                    "{} {},{}",
-                    format_extend_op(signed, from_bits, to_bits),
-                    rm,
-                    rn
-                )
+                let rd = format_reg(rd.to_reg(), allocs);
+                return if signed == false && from_bits == 8 {
+                    format!("andi {rd},{rn}")
+                } else {
+                    let op = if signed { "srai" } else { "srli" };
+                    let shift_bits = (64 - from_bits) as i16;
+                    format!("slli {rd},{rn},{shift_bits}; {op} {rd},{rd},{shift_bits}")
+                };
             }
             &MInst::AjustSp { amount } => {
                 format!("{} sp,{:+}", "add", amount)

cranelift/codegen/src/isa/riscv64/lower.isle

@@ -328,12 +328,12 @@
   (lower_clz_i128 x))
 
 ;;;; Rules for `uextend` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-(rule (lower (has_type out (uextend x @ (value_type in))))
-  (lower_extend x $false (ty_bits in) (ty_bits out)))
+(rule (lower (has_type out_ty (uextend val @ (value_type in_ty))))
+  (zext val in_ty out_ty))
 
 ;;;; Rules for `sextend` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-(rule (lower (has_type out (sextend x @ (value_type in))))
-  (lower_extend x $true (ty_bits in) (ty_bits out)))
+(rule (lower (has_type out_ty (sextend val @ (value_type in_ty))))
+  (sext val in_ty out_ty))
 
 
 ;;;; Rules for `popcnt` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

cranelift/codegen/src/isa/riscv64/lower/isle.rs

@@ -229,17 +229,6 @@ impl generated_code::Context for IsleContext<'_, '_, MInst, Riscv64Backend> {
         x as i32
     }
 
-    fn ext_sign_bit(&mut self, ty: Type, r: Reg) -> Reg {
-        assert!(ty.is_int());
-        let rd = self.temp_writable_reg(I64);
-        self.emit(&MInst::AluRRImm12 {
-            alu_op: AluOPRRI::Bexti,
-            rd,
-            rs: r,
-            imm12: Imm12::from_bits((ty.bits() - 1) as i16),
-        });
-        rd.to_reg()
-    }
     fn imm12_const(&mut self, val: i32) -> Imm12 {
         if let Some(res) = Imm12::maybe_from_u64(val as u64) {
             res

cranelift/filetests/filetests/isa/riscv64/amodes.clif

@@ -19,8 +19,7 @@ block0(v0: i64, v1: i32):
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   slli a2, a1, 0x20
-;   srai a2, a2, 0x20
+;   sext.w a2, a1
 ;   add a2, a0, a2
 ;   lw a0, 0(a2)
 ;   ret
@@ -42,8 +41,7 @@ block0(v0: i64, v1: i32):
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   slli a2, a1, 0x20
-;   srai a2, a2, 0x20
+;   sext.w a2, a1
 ;   add a2, a2, a0
 ;   lw a0, 0(a2)
 ;   ret
@@ -59,20 +57,22 @@ block0(v0: i32, v1: i32):
 
 ; VCode:
 ; block0:
-;   uext.w a3,a0
-;   uext.w a4,a1
-;   add a3,a3,a4
-;   lw a0,0(a3)
+;   slli a4,a0,32
+;   srli a6,a4,32
+;   slli a4,a1,32
+;   srli a7,a4,32
+;   add a5,a6,a7
+;   lw a0,0(a5)
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   slli a3, a0, 0x20
-;   srli a3, a3, 0x20
+;   slli a4, a0, 0x20
+;   srli a6, a4, 0x20
 ;   slli a4, a1, 0x20
-;   srli a4, a4, 0x20
-;   add a3, a3, a4
-;   lw a0, 0(a3)
+;   srli a7, a4, 0x20
+;   add a5, a6, a7
+;   lw a0, 0(a5)
 ;   ret
 
 function %f8(i64, i32) -> i32 {
@@ -97,8 +97,7 @@ block0(v0: i64, v1: i32):
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   slli a4, a1, 0x20
-;   srai a4, a4, 0x20
+;   sext.w a4, a1
 ;   addi a4, a4, 0x20
 ;   add a4, a4, a0
 ;   add a4, a4, a4
@@ -261,8 +260,7 @@ block0(v0: i32):
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   slli a0, a0, 0x20
-;   srai a0, a0, 0x20
+;   sext.w a0, a0
 ;   lw a0, 0(a0)
 ;   ret
 
@@ -285,10 +283,8 @@ block0(v0: i32, v1: i32):
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   slli a3, a0, 0x20
-;   srai a3, a3, 0x20
-;   slli a4, a1, 0x20
-;   srai a4, a4, 0x20
+;   sext.w a3, a0
+;   sext.w a4, a1
 ;   add a3, a3, a4
 ;   lw a0, 0(a3)
 ;   ret
@@ -305,8 +301,9 @@ block0(v0: i64, v1: i64, v2: i64):
 ; block0:
 ;   lui a3,1048575
 ;   addi a3,a3,4094
-;   uext.w a6,a3
-;   lh a0,0(a6)
+;   slli a6,a3,32
+;   srli t3,a6,32
+;   lh a0,0(t3)
 ;   ret
 ; 
 ; Disassembled:
@@ -314,8 +311,8 @@ block0(v0: i64, v1: i64, v2: i64):
 ;   lui a3, 0xfffff
 ;   addi a3, a3, -2
 ;   slli a6, a3, 0x20
-;   srli a6, a6, 0x20
-;   lh a0, 0(a6)
+;   srli t3, a6, 0x20
+;   lh a0, 0(t3)
 ;   ret
 
 function %f19(i64, i64, i64) -> i32 {
@@ -330,8 +327,9 @@ block0(v0: i64, v1: i64, v2: i64):
 ; block0:
 ;   lui a3,1
 ;   addi a3,a3,2
-;   uext.w a6,a3
-;   lh a0,0(a6)
+;   slli a6,a3,32
+;   srli t3,a6,32
+;   lh a0,0(t3)
 ;   ret
 ; 
 ; Disassembled:
@@ -339,8 +337,8 @@ block0(v0: i64, v1: i64, v2: i64):
 ;   lui a3, 1
 ;   addi a3, a3, 2
 ;   slli a6, a3, 0x20
-;   srli a6, a6, 0x20
-;   lh a0, 0(a6)
+;   srli t3, a6, 0x20
+;   lh a0, 0(t3)
 ;   ret
 
 function %f20(i64, i64, i64) -> i32 {
@@ -363,8 +361,7 @@ block0(v0: i64, v1: i64, v2: i64):
 ; block0: ; offset 0x0
 ;   lui a3, 0xfffff
 ;   addi a3, a3, -2
-;   slli a6, a3, 0x20
-;   srai a6, a6, 0x20
+;   sext.w a6, a3
 ;   lh a0, 0(a6)
 ;   ret
 
@@ -388,8 +385,7 @@ block0(v0: i64, v1: i64, v2: i64):
 ; block0: ; offset 0x0
 ;   lui a3, 1
 ;   addi a3, a3, 2
-;   slli a6, a3, 0x20
-;   srai a6, a6, 0x20
+;   sext.w a6, a3
 ;   lh a0, 0(a6)
 ;   ret
 
@@ -554,8 +550,7 @@ block0(v0: i32):
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   slli a2, a0, 0x20
-;   srai a2, a2, 0x20
+;   sext.w a2, a0
 ;   ld a0, 0(a2)
 ;   ld a1, 8(a2)
 ;   sd a0, 0(a2)
@@ -585,8 +580,7 @@ block0(v0: i64, v1: i32):
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   slli a4, a1, 0x20
-;   srai a4, a4, 0x20
+;   sext.w a4, a1
 ;   add a4, a0, a4
 ;   addi a4, a4, 0x18
 ;   ld a0, 0(a4)

cranelift/filetests/filetests/isa/riscv64/arithmetic.clif

@@ -274,10 +274,8 @@ block0(v0: i32, v1: i32):
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   slli a0, a0, 0x20
-;   srai a0, a0, 0x20
-;   slli a2, a1, 0x20
-;   srai a2, a2, 0x20
+;   sext.w a0, a0
+;   sext.w a2, a1
 ;   addi a4, zero, -1
 ;   addi a6, zero, 1
 ;   slli t3, a6, 0x3f
@@ -324,11 +322,9 @@ block0(v0: i32):
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   slli t2, a0, 0x20
-;   srai t2, t2, 0x20
+;   sext.w t2, a0
 ;   addi a1, zero, 2
-;   slli a3, a1, 0x20
-;   srai a3, a3, 0x20
+;   sext.w a3, a1
 ;   addi a5, zero, -1
 ;   addi a7, zero, 1
 ;   slli t4, a7, 0x3f
@@ -357,23 +353,23 @@ block0(v0: i32, v1: i32):
 
 ; VCode:
 ; block0:
-;   mv a5,a0
-;   uext.w a0,a1
-;   trap_ifc int_divz##(zero eq a0)
-;   uext.w a3,a5
-;   divuw a0,a3,a0
+;   slli a1,a1,32
+;   srli a2,a1,32
+;   trap_ifc int_divz##(zero eq a2)
+;   slli a5,a0,32
+;   srli a7,a5,32
+;   divuw a0,a7,a2
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   ori a5, a0, 0
-;   slli a0, a1, 0x20
-;   srli a0, a0, 0x20
-;   bne zero, a0, 8
+;   slli a1, a1, 0x20
+;   srli a2, a1, 0x20
+;   bne zero, a2, 8
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: int_divz
-;   slli a3, a5, 0x20
-;   srli a3, a3, 0x20
-;   divuw a0, a3, a0
+;   slli a5, a0, 0x20
+;   srli a7, a5, 0x20
+;   divuw a0, a7, a2
 ;   ret
 
 function %f15(i32) -> i32 {
@@ -386,22 +382,24 @@ block0(v0: i32):
 ; VCode:
 ; block0:
 ;   li t2,2
-;   uext.w a1,t2
-;   trap_ifc int_divz##(zero eq a1)
-;   uext.w a4,a0
-;   divuw a0,a4,a1
+;   slli a1,t2,32
+;   srli a3,a1,32
+;   trap_ifc int_divz##(zero eq a3)
+;   slli a6,a0,32
+;   srli t3,a6,32
+;   divuw a0,t3,a3
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
 ;   addi t2, zero, 2
 ;   slli a1, t2, 0x20
-;   srli a1, a1, 0x20
-;   bne zero, a1, 8
+;   srli a3, a1, 0x20
+;   bne zero, a3, 8
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: int_divz
-;   slli a4, a0, 0x20
-;   srli a4, a4, 0x20
-;   divuw a0, a4, a1
+;   slli a6, a0, 0x20
+;   srli t3, a6, 0x20
+;   divuw a0, t3, a3
 ;   ret
 
 function %f16(i32, i32) -> i32 {
@@ -419,8 +417,7 @@ block0(v0: i32, v1: i32):
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   slli a1, a1, 0x20
-;   srai a1, a1, 0x20
+;   sext.w a1, a1
 ;   bne zero, a1, 8
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: int_divz
 ;   remw a0, a0, a1
@@ -434,18 +431,19 @@ block0(v0: i32, v1: i32):
 
 ; VCode:
 ; block0:
-;   uext.w a1,a1
-;   trap_ifc int_divz##(zero eq a1)
-;   remuw a0,a0,a1
+;   slli a1,a1,32
+;   srli a2,a1,32
+;   trap_ifc int_divz##(zero eq a2)
+;   remuw a0,a0,a2
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
 ;   slli a1, a1, 0x20
-;   srli a1, a1, 0x20
-;   bne zero, a1, 8
+;   srli a2, a1, 0x20
+;   bne zero, a2, 8
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: int_divz
-;   remuw a0, a0, a1
+;   remuw a0, a0, a2
 ;   ret
 
 function %f18(i64, i64) -> i64 {

cranelift/filetests/filetests/isa/riscv64/atomic_load.clif

@@ -47,16 +47,17 @@ block0(v0: i64):
 
 ; VCode:
 ; block0:
-;   atomic_load.i32 a0,(a0)
-;   uext.w a0,a0
+;   atomic_load.i32 a1,(a0)
+;   slli a0,a1,32
+;   srli a0,a0,32
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
 ;   fence rw, rw
-;   lw a0, 0(a0)
+;   lw a1, 0(a0)
 ;   fence r, rw
-;   slli a0, a0, 0x20
+;   slli a0, a1, 0x20
 ;   srli a0, a0, 0x20
 ;   ret
 

cranelift/filetests/filetests/isa/riscv64/bitops.clif

@@ -436,34 +436,35 @@ block0(v0: i8):
 
 ; VCode:
 ; block0:
-;   sext.b t2,a0
-;   not a1,a0
-;   select_reg a3,a1,a0##condition=(t2 slt zero)
-;   clz a7,a3##ty=i8 tmp=a5 step=a6
-;   addi a0,a7,-1
+;   slli t2,a0,56
+;   srai a1,t2,56
+;   not a3,a0
+;   select_reg a5,a3,a0##condition=(a1 slt zero)
+;   clz t4,a5##ty=i8 tmp=a7 step=t3
+;   addi a0,t4,-1
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
 ;   slli t2, a0, 0x38
-;   srai t2, t2, 0x38
-;   not a1, a0
-;   bltz t2, 0xc
-;   ori a3, a0, 0
+;   srai a1, t2, 0x38
+;   not a3, a0
+;   bltz a1, 0xc
+;   ori a5, a0, 0
 ;   j 8
-;   ori a3, a1, 0
-;   ori a7, zero, 0
-;   addi a6, zero, 8
-;   addi a5, zero, 1
-;   slli a5, a5, 7
-;   blez a6, 0x1c
-;   and t5, a5, a3
+;   ori a5, a3, 0
+;   ori t4, zero, 0
+;   addi t3, zero, 8
+;   addi a7, zero, 1
+;   slli a7, a7, 7
+;   blez t3, 0x1c
+;   and t5, a7, a5
 ;   bne zero, t5, 0x14
-;   addi a7, a7, 1
-;   addi a6, a6, -1
-;   srli a5, a5, 1
+;   addi t4, t4, 1
+;   addi t3, t3, -1
+;   srli a7, a7, 1
 ;   j -0x18
-;   addi a0, a7, -1
+;   addi a0, t4, -1
 ;   ret
 
 function %c(i16) -> i16 {
@@ -474,34 +475,35 @@ block0(v0: i16):
 
 ; VCode:
 ; block0:
-;   sext.h t2,a0
-;   not a1,a0
-;   select_reg a3,a1,a0##condition=(t2 slt zero)
-;   clz a7,a3##ty=i16 tmp=a5 step=a6
-;   addi a0,a7,-1
+;   slli t2,a0,48
+;   srai a1,t2,48
+;   not a3,a0
+;   select_reg a5,a3,a0##condition=(a1 slt zero)
+;   clz t4,a5##ty=i16 tmp=a7 step=t3
+;   addi a0,t4,-1
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
 ;   slli t2, a0, 0x30
-;   srai t2, t2, 0x30
-;   not a1, a0
-;   bltz t2, 0xc
-;   ori a3, a0, 0
+;   srai a1, t2, 0x30
+;   not a3, a0
+;   bltz a1, 0xc
+;   ori a5, a0, 0
 ;   j 8
-;   ori a3, a1, 0
-;   ori a7, zero, 0
-;   addi a6, zero, 0x10
-;   addi a5, zero, 1
-;   slli a5, a5, 0xf
-;   blez a6, 0x1c
-;   and t5, a5, a3
+;   ori a5, a3, 0
+;   ori t4, zero, 0
+;   addi t3, zero, 0x10
+;   addi a7, zero, 1
+;   slli a7, a7, 0xf
+;   blez t3, 0x1c
+;   and t5, a7, a5
 ;   bne zero, t5, 0x14
-;   addi a7, a7, 1
-;   addi a6, a6, -1
-;   srli a5, a5, 1
+;   addi t4, t4, 1
+;   addi t3, t3, -1
+;   srli a7, a7, 1
 ;   j -0x18
-;   addi a0, a7, -1
+;   addi a0, t4, -1
 ;   ret
 
 function %c(i32) -> i32 {
@@ -521,8 +523,7 @@ block0(v0: i32):
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   slli t2, a0, 0x20
-;   srai t2, t2, 0x20
+;   sext.w t2, a0
 ;   not a1, a0
 ;   bltz t2, 0xc
 ;   ori a3, a0, 0

cranelift/filetests/filetests/isa/riscv64/call.clif

@@ -55,7 +55,7 @@ block0(v0: i32):
 ;   sd fp,0(sp)
 ;   mv fp,sp
 ; block0:
-;   uext.w a0,a0
+;   slli a0,a0,32; srli a0,a0,32
 ;   load_sym a2,%g+0
 ;   callind a2
 ;   ld ra,8(sp)
@@ -90,7 +90,7 @@ block0(v0: i32):
 
 ; VCode:
 ; block0:
-;   uext.w a0,a0
+;   slli a0,a0,32; srli a0,a0,32
 ;   ret
 ; 
 ; Disassembled:
@@ -113,7 +113,7 @@ block0(v0: i32):
 ;   sd fp,0(sp)
 ;   mv fp,sp
 ; block0:
-;   sext.w a0,a0
+;   slli a0,a0,32; srai a0,a0,32
 ;   load_sym a2,%g+0
 ;   callind a2
 ;   ld ra,8(sp)
@@ -148,7 +148,7 @@ block0(v0: i32):
 
 ; VCode:
 ; block0:
-;   sext.w a0,a0
+;   slli a0,a0,32; srai a0,a0,32
 ;   ret
 ; 
 ; Disassembled:
@@ -183,7 +183,7 @@ block0(v0: i8):
 ;   li a5,42
 ;   li a6,42
 ;   li a7,42
-;   sext.b t3,t3
+;   slli t3,t3,56; srai t3,t3,56
 ;   sd t3,0(sp)
 ;   load_sym t3,%g+0
 ;   callind t3
@@ -250,7 +250,7 @@ block0(v0: i8):
 ;   sw t0,24(a1)
 ;   sw t2,32(a1)
 ;   sw a2,40(a1)
-;   sext.b t4,a0
+;   slli t4,a0,56; srai t4,t4,56
 ;   sd a0,48(a1)
 ;   mv a0,t1
 ;   mv a1,a3

cranelift/filetests/filetests/isa/riscv64/condbr.clif

@@ -705,7 +705,7 @@ block1:
 
 ; VCode:
 ; block0:
-;   addiw t2,a0,0
+;   sext.w t2,a0
 ;   bne t2,zero,taken(label1),not_taken(label2)
 ; block1:
 ;   j label3

cranelift/filetests/filetests/isa/riscv64/condops.clif

@@ -39,8 +39,8 @@ block0(v0: i8):
 ; VCode:
 ; block0:
 ;   li t2,42
-;   uext.b a1,a0
-;   uext.b a3,t2
+;   andi a1,a0,255
+;   andi a3,t2,255
 ;   eq a0,a1,a3##ty=i8
 ;   ret
 ; 
@@ -108,9 +108,9 @@ block0(v0: i32, v1: i8, v2: i8):
 
 ; VCode:
 ; block0:
-;   addiw a3,a0,0
+;   sext.w a3,a0
 ;   li a4,42
-;   addiw a5,a4,0
+;   sext.w a5,a4
 ;   select_reg a0,a1,a2##condition=(a3 eq a5)
 ;   ret
 ; 

cranelift/filetests/filetests/isa/riscv64/extend-i128.clif

@@ -0,0 +1,152 @@
+test compile precise-output
+set unwind_info=false
+target riscv64
+
+function %uextend_i64_i128(i64) -> i128 {
+block0(v0: i64):
+    v1 = uextend.i128 v0
+    return v1
+}
+
+; VCode:
+; block0:
+;   li a1,0
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   mv a1, zero
+;   ret
+
+function %uextend_i32_i128(i32) -> i128 {
+block0(v0: i32):
+    v1 = uextend.i128 v0
+    return v1
+}
+
+; VCode:
+; block0:
+;   slli t2,a0,32
+;   srli a0,t2,32
+;   li a1,0
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli t2, a0, 0x20
+;   srli a0, t2, 0x20
+;   mv a1, zero
+;   ret
+
+function %uextend_i16_i128(i16) -> i128 {
+block0(v0: i16):
+    v1 = uextend.i128 v0
+    return v1
+}
+
+; VCode:
+; block0:
+;   slli t2,a0,48
+;   srli a0,t2,48
+;   li a1,0
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli t2, a0, 0x30
+;   srli a0, t2, 0x30
+;   mv a1, zero
+;   ret
+
+function %uextend_i8_i128(i8) -> i128 {
+block0(v0: i8):
+    v1 = uextend.i128 v0
+    return v1
+}
+
+; VCode:
+; block0:
+;   andi a0,a0,255
+;   li a1,0
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   andi a0, a0, 0xff
+;   mv a1, zero
+;   ret
+
+function %sextend_i64_i128(i64) -> i128 {
+block0(v0: i64):
+    v1 = sextend.i128 v0
+    return v1
+}
+
+; VCode:
+; block0:
+;   srai a1,a0,63
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   srai a1, a0, 0x3f
+;   ret
+
+function %sextend_i32_i128(i32) -> i128 {
+block0(v0: i32):
+    v1 = sextend.i128 v0
+    return v1
+}
+
+; VCode:
+; block0:
+;   sext.w a0,a0
+;   srai a1,a0,63
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sext.w a0, a0
+;   srai a1, a0, 0x3f
+;   ret
+
+function %sextend_i16_i128(i16) -> i128 {
+block0(v0: i16):
+    v1 = sextend.i128 v0
+    return v1
+}
+
+; VCode:
+; block0:
+;   slli t2,a0,48
+;   srai a0,t2,48
+;   srai a1,a0,63
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli t2, a0, 0x30
+;   srai a0, t2, 0x30
+;   srai a1, a0, 0x3f
+;   ret
+
+function %sextend_i8_i128(i8) -> i128 {
+block0(v0: i8):
+    v1 = sextend.i128 v0
+    return v1
+}
+
+; VCode:
+; block0:
+;   slli t2,a0,56
+;   srai a0,t2,56
+;   srai a1,a0,63
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli t2, a0, 0x38
+;   srai a0, t2, 0x38
+;   srai a1, a0, 0x3f
+;   ret
+

cranelift/filetests/filetests/isa/riscv64/extend-op.clif

@@ -1,202 +0,0 @@
-test compile precise-output
-set unwind_info=false
-target riscv64
-
-function %f(i8) -> i64 {
-block0(v0: i8):
-  v1 = sextend.i64 v0
-  v2 = iconst.i64 42
-  v3 = iadd.i64 v2, v1
-  return v3
-}
-
-; VCode:
-; block0:
-;   sext.b a0,a0
-;   addi a0,a0,42
-;   ret
-; 
-; Disassembled:
-; block0: ; offset 0x0
-;   slli a0, a0, 0x38
-;   srai a0, a0, 0x38
-;   addi a0, a0, 0x2a
-;   ret
-
-function %f2(i8, i64) -> i64 {
-block0(v0: i8, v1: i64):
-  v2 = sextend.i64 v0
-  v3 = iadd.i64 v2, v1
-  return v3
-}
-
-; VCode:
-; block0:
-;   sext.b a2,a0
-;   add a0,a2,a1
-;   ret
-; 
-; Disassembled:
-; block0: ; offset 0x0
-;   slli a2, a0, 0x38
-;   srai a2, a2, 0x38
-;   add a0, a2, a1
-;   ret
-
-function %i128_uextend_i64(i64) -> i128 {
-block0(v0: i64):
-    v1 = uextend.i128 v0
-    return v1
-}
-
-; VCode:
-; block0:
-;   li a1,0
-;   ret
-; 
-; Disassembled:
-; block0: ; offset 0x0
-;   mv a1, zero
-;   ret
-
-function %i128_sextend_i64(i64) -> i128 {
-block0(v0: i64):
-    v1 = sextend.i128 v0
-    return v1
-}
-
-; VCode:
-; block0:
-;   slt t2,a0,zero
-;   sext.b1 a1,t2
-;   ret
-; 
-; Disassembled:
-; block0: ; offset 0x0
-;   sltz t2, a0
-;   slli a1, t2, 0x3f
-;   srai a1, a1, 0x3f
-;   ret
-
-function %i128_uextend_i32(i32) -> i128 {
-block0(v0: i32):
-    v1 = uextend.i128 v0
-    return v1
-}
-
-; VCode:
-; block0:
-;   uext.w a0,a0
-;   li a1,0
-;   ret
-; 
-; Disassembled:
-; block0: ; offset 0x0
-;   slli a0, a0, 0x20
-;   srli a0, a0, 0x20
-;   mv a1, zero
-;   ret
-
-function %i128_sextend_i32(i32) -> i128 {
-block0(v0: i32):
-    v1 = sextend.i128 v0
-    return v1
-}
-
-; VCode:
-; block0:
-;   sext.w a0,a0
-;   slt a1,a0,zero
-;   sext.b1 a1,a1
-;   ret
-; 
-; Disassembled:
-; block0: ; offset 0x0
-;   slli a0, a0, 0x20
-;   srai a0, a0, 0x20
-;   sltz a1, a0
-;   slli a1, a1, 0x3f
-;   srai a1, a1, 0x3f
-;   ret
-
-function %i128_uextend_i16(i16) -> i128 {
-block0(v0: i16):
-    v1 = uextend.i128 v0
-    return v1
-}
-
-; VCode:
-; block0:
-;   uext.h a0,a0
-;   li a1,0
-;   ret
-; 
-; Disassembled:
-; block0: ; offset 0x0
-;   slli a0, a0, 0x30
-;   srli a0, a0, 0x30
-;   mv a1, zero
-;   ret
-
-function %i128_sextend_i16(i16) -> i128 {
-block0(v0: i16):
-    v1 = sextend.i128 v0
-    return v1
-}
-
-; VCode:
-; block0:
-;   sext.h a0,a0
-;   slt a1,a0,zero
-;   sext.b1 a1,a1
-;   ret
-; 
-; Disassembled:
-; block0: ; offset 0x0
-;   slli a0, a0, 0x30
-;   srai a0, a0, 0x30
-;   sltz a1, a0
-;   slli a1, a1, 0x3f
-;   srai a1, a1, 0x3f
-;   ret
-
-function %i128_uextend_i8(i8) -> i128 {
-block0(v0: i8):
-    v1 = uextend.i128 v0
-    return v1
-}
-
-; VCode:
-; block0:
-;   uext.b a0,a0
-;   li a1,0
-;   ret
-; 
-; Disassembled:
-; block0: ; offset 0x0
-;   andi a0, a0, 0xff
-;   mv a1, zero
-;   ret
-
-function %i128_sextend_i8(i8) -> i128 {
-block0(v0: i8):
-    v1 = sextend.i128 v0
-    return v1
-}
-
-; VCode:
-; block0:
-;   sext.b a0,a0
-;   slt a1,a0,zero
-;   sext.b1 a1,a1
-;   ret
-; 
-; Disassembled:
-; block0: ; offset 0x0
-;   slli a0, a0, 0x38
-;   srai a0, a0, 0x38
-;   sltz a1, a0
-;   slli a1, a1, 0x3f
-;   srai a1, a1, 0x3f
-;   ret
-

cranelift/filetests/filetests/isa/riscv64/extend-zbb.clif

@@ -0,0 +1,136 @@
+test compile precise-output
+set unwind_info=false
+target riscv64 has_zbb=true
+
+
+;;;; Uextend rules
+
+function %uextend16_32(i16) -> i32 {
+block0(v0: i16):
+    v1 = uextend.i32 v0
+    return v1
+}
+
+; VCode:
+; block0:
+;   zext.h a0,a0
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0x3b, 0x45, 0x05, 0x08
+;   ret
+
+function %uextend8_64(i8) -> i64 {
+block0(v0: i8):
+    v1 = uextend.i64 v0
+    return v1
+}
+
+; VCode:
+; block0:
+;   andi a0,a0,255
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   andi a0, a0, 0xff
+;   ret
+
+function %uextend16_64(i16) -> i64 {
+block0(v0: i16):
+    v1 = uextend.i64 v0
+    return v1
+}
+
+; VCode:
+; block0:
+;   zext.h a0,a0
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0x3b, 0x45, 0x05, 0x08
+;   ret
+
+;;;; Sextend Rules
+
+function %sextend8_16(i8) -> i16 {
+block0(v0: i8):
+    v1 = sextend.i16 v0
+    return v1
+}
+
+; VCode:
+; block0:
+;   sext.b a0,a0
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0x13, 0x15, 0x45, 0x60
+;   ret
+
+function %sextend8_32(i8) -> i32 {
+block0(v0: i8):
+    v1 = sextend.i32 v0
+    return v1
+}
+
+; VCode:
+; block0:
+;   sext.b a0,a0
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0x13, 0x15, 0x45, 0x60
+;   ret
+
+function %sextend16_32(i16) -> i32 {
+block0(v0: i16):
+    v1 = sextend.i32 v0
+    return v1
+}
+
+; VCode:
+; block0:
+;   sext.h a0,a0
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0x13, 0x15, 0x55, 0x60
+;   ret
+
+function %sextend8_64(i8) -> i64 {
+block0(v0: i8):
+    v1 = sextend.i64 v0
+    return v1
+}
+
+; VCode:
+; block0:
+;   sext.b a0,a0
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0x13, 0x15, 0x45, 0x60
+;   ret
+
+function %sextend16_64(i16) -> i64 {
+block0(v0: i16):
+    v1 = sextend.i64 v0
+    return v1
+}
+
+; VCode:
+; block0:
+;   sext.h a0,a0
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0x13, 0x15, 0x55, 0x60
+;   ret

cranelift/filetests/filetests/isa/riscv64/extend-zbkb.clif

@@ -0,0 +1,53 @@
+test compile precise-output
+set unwind_info=false
+target riscv64 has_zbkb=true
+
+
+function %uextend16_32(i16) -> i32 {
+block0(v0: i16):
+    v1 = uextend.i32 v0
+    return v1
+}
+
+; VCode:
+; block0:
+;   packw a0,a0,zero
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0x3b, 0x45, 0x05, 0x08
+;   ret
+
+function %uextend16_64(i16) -> i64 {
+block0(v0: i16):
+    v1 = uextend.i64 v0
+    return v1
+}
+
+; VCode:
+; block0:
+;   packw a0,a0,zero
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0x3b, 0x45, 0x05, 0x08
+;   ret
+
+function %uextend32_64(i32) -> i64 {
+block0(v0: i32):
+    v1 = uextend.i64 v0
+    return v1
+}
+
+; VCode:
+; block0:
+;   pack a0,a0,zero
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0x33, 0x45, 0x05, 0x08
+;   ret
+

cranelift/filetests/filetests/isa/riscv64/extend.clif

@@ -0,0 +1,260 @@
+test compile precise-output
+set unwind_info=false
+target riscv64
+
+
+;;;; Uextend rules
+
+function %uextend8_16(i8) -> i16 {
+block0(v0: i8):
+    v1 = uextend.i16 v0
+    return v1
+}
+
+; VCode:
+; block0:
+;   andi a0,a0,255
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   andi a0, a0, 0xff
+;   ret
+
+function %uextend8_32(i8) -> i32 {
+block0(v0: i8):
+    v1 = uextend.i32 v0
+    return v1
+}
+
+; VCode:
+; block0:
+;   andi a0,a0,255
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   andi a0, a0, 0xff
+;   ret
+
+function %uextend16_32(i16) -> i32 {
+block0(v0: i16):
+    v1 = uextend.i32 v0
+    return v1
+}
+
+; VCode:
+; block0:
+;   slli t2,a0,48
+;   srli a0,t2,48
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli t2, a0, 0x30
+;   srli a0, t2, 0x30
+;   ret
+
+function %uextend8_64(i8) -> i64 {
+block0(v0: i8):
+    v1 = uextend.i64 v0
+    return v1
+}
+
+; VCode:
+; block0:
+;   andi a0,a0,255
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   andi a0, a0, 0xff
+;   ret
+
+function %uextend16_64(i16) -> i64 {
+block0(v0: i16):
+    v1 = uextend.i64 v0
+    return v1
+}
+
+; VCode:
+; block0:
+;   slli t2,a0,48
+;   srli a0,t2,48
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli t2, a0, 0x30
+;   srli a0, t2, 0x30
+;   ret
+
+function %uextend32_64(i32) -> i64 {
+block0(v0: i32):
+    v1 = uextend.i64 v0
+    return v1
+}
+
+; VCode:
+; block0:
+;   slli t2,a0,32
+;   srli a0,t2,32
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli t2, a0, 0x20
+;   srli a0, t2, 0x20
+;   ret
+
+;;;; Sextend Rules
+
+function %sextend8_16(i8) -> i16 {
+block0(v0: i8):
+    v1 = sextend.i16 v0
+    return v1
+}
+
+; VCode:
+; block0:
+;   slli t2,a0,56
+;   srai a0,t2,56
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli t2, a0, 0x38
+;   srai a0, t2, 0x38
+;   ret
+
+function %sextend8_32(i8) -> i32 {
+block0(v0: i8):
+    v1 = sextend.i32 v0
+    return v1
+}
+
+; VCode:
+; block0:
+;   slli t2,a0,56
+;   srai a0,t2,56
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli t2, a0, 0x38
+;   srai a0, t2, 0x38
+;   ret
+
+function %sextend16_32(i16) -> i32 {
+block0(v0: i16):
+    v1 = sextend.i32 v0
+    return v1
+}
+
+; VCode:
+; block0:
+;   slli t2,a0,48
+;   srai a0,t2,48
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli t2, a0, 0x30
+;   srai a0, t2, 0x30
+;   ret
+
+function %sextend8_64(i8) -> i64 {
+block0(v0: i8):
+    v1 = sextend.i64 v0
+    return v1
+}
+
+; VCode:
+; block0:
+;   slli t2,a0,56
+;   srai a0,t2,56
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli t2, a0, 0x38
+;   srai a0, t2, 0x38
+;   ret
+
+function %sextend16_64(i16) -> i64 {
+block0(v0: i16):
+    v1 = sextend.i64 v0
+    return v1
+}
+
+; VCode:
+; block0:
+;   slli t2,a0,48
+;   srai a0,t2,48
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli t2, a0, 0x30
+;   srai a0, t2, 0x30
+;   ret
+
+function %sextend32_64(i32) -> i64 {
+block0(v0: i32):
+    v1 = sextend.i64 v0
+    return v1
+}
+
+; VCode:
+; block0:
+;   sext.w a0,a0
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sext.w a0, a0
+;   ret
+
+function %f(i8) -> i64 {
+block0(v0: i8):
+  v1 = sextend.i64 v0
+  v2 = iconst.i64 42
+  v3 = iadd.i64 v2, v1
+  return v3
+}
+
+; VCode:
+; block0:
+;   slli a0,a0,56
+;   srai a2,a0,56
+;   addi a0,a2,42
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli a0, a0, 0x38
+;   srai a2, a0, 0x38
+;   addi a0, a2, 0x2a
+;   ret
+
+function %f2(i8, i64) -> i64 {
+block0(v0: i8, v1: i64):
+  v2 = sextend.i64 v0
+  v3 = iadd.i64 v2, v1
+  return v3
+}
+
+; VCode:
+; block0:
+;   slli a2,a0,56
+;   srai a3,a2,56
+;   add a0,a3,a1
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli a2, a0, 0x38
+;   srai a3, a2, 0x38
+;   add a0, a3, a1
+;   ret
+

cranelift/filetests/filetests/isa/riscv64/i128-bmask.clif

@@ -150,7 +150,7 @@ block0(v0: i32):
 
 ; VCode:
 ; block0:
-;   addiw t2,a0,0
+;   sext.w t2,a0
 ;   li a1,-1
 ;   select_reg a1,zero,a1##condition=(zero eq t2)
 ;   mv a0,a1

cranelift/filetests/filetests/isa/riscv64/iabs-zbb.clif

@@ -16,8 +16,7 @@ block0(v0: i8):
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   slli t2, a0, 0x38
-;   srai t2, t2, 0x38
+;   .byte 0x93, 0x13, 0x45, 0x60
 ;   neg a1, t2
 ;   .byte 0x33, 0xe5, 0xb3, 0x0a
 ;   ret
@@ -37,8 +36,7 @@ block0(v0: i16):
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   slli t2, a0, 0x30
-;   srai t2, t2, 0x30
+;   .byte 0x93, 0x13, 0x55, 0x60
 ;   neg a1, t2
 ;   .byte 0x33, 0xe5, 0xb3, 0x0a
 ;   ret
@@ -58,8 +56,7 @@ block0(v0: i32):
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   slli t2, a0, 0x20
-;   srai t2, t2, 0x20
+;   sext.w t2, a0
 ;   neg a1, t2
 ;   .byte 0x33, 0xe5, 0xb3, 0x0a
 ;   ret

cranelift/filetests/filetests/isa/riscv64/iabs.clif

@@ -9,20 +9,21 @@ block0(v0: i8):
 
 ; VCode:
 ; block0:
-;   sext.b t2,a0
-;   sub a1,zero,t2
-;   select_reg a0,t2,a1##condition=(t2 sgt a1)
+;   slli t2,a0,56
+;   srai a1,t2,56
+;   sub a3,zero,a1
+;   select_reg a0,a1,a3##condition=(a1 sgt a3)
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
 ;   slli t2, a0, 0x38
-;   srai t2, t2, 0x38
-;   neg a1, t2
-;   blt a1, t2, 0xc
-;   ori a0, a1, 0
+;   srai a1, t2, 0x38
+;   neg a3, a1
+;   blt a3, a1, 0xc
+;   ori a0, a3, 0
 ;   j 8
-;   ori a0, t2, 0
+;   ori a0, a1, 0
 ;   ret
 
 function %iabs_i16(i16) -> i16 {
@@ -33,20 +34,21 @@ block0(v0: i16):
 
 ; VCode:
 ; block0:
-;   sext.h t2,a0
-;   sub a1,zero,t2
-;   select_reg a0,t2,a1##condition=(t2 sgt a1)
+;   slli t2,a0,48
+;   srai a1,t2,48
+;   sub a3,zero,a1
+;   select_reg a0,a1,a3##condition=(a1 sgt a3)
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
 ;   slli t2, a0, 0x30
-;   srai t2, t2, 0x30
-;   neg a1, t2
-;   blt a1, t2, 0xc
-;   ori a0, a1, 0
+;   srai a1, t2, 0x30
+;   neg a3, a1
+;   blt a3, a1, 0xc
+;   ori a0, a3, 0
 ;   j 8
-;   ori a0, t2, 0
+;   ori a0, a1, 0
 ;   ret
 
 function %iabs_i32(i32) -> i32 {
@@ -64,8 +66,7 @@ block0(v0: i32):
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   slli t2, a0, 0x20
-;   srai t2, t2, 0x20
+;   sext.w t2, a0
 ;   neg a1, t2
 ;   blt a1, t2, 0xc
 ;   ori a0, a1, 0

cranelift/filetests/filetests/isa/riscv64/iconst-icmp-small.clif

@@ -16,9 +16,11 @@ block0:
 ;   addi t1,t1,3532
 ;   lui a2,14
 ;   addi a2,a2,3532
-;   uext.h a5,t1
-;   uext.h a7,a2
-;   ne a0,a5,a7##ty=i16
+;   slli a5,t1,48
+;   srli a7,a5,48
+;   slli t4,a2,48
+;   srli t1,t4,48
+;   ne a0,a7,t1##ty=i16
 ;   ret
 ; 
 ; Disassembled:
@@ -28,10 +30,10 @@ block0:
 ;   lui a2, 0xe
 ;   addi a2, a2, -0x234
 ;   slli a5, t1, 0x30
-;   srli a5, a5, 0x30
-;   slli a7, a2, 0x30
-;   srli a7, a7, 0x30
-;   beq a5, a7, 0xc
+;   srli a7, a5, 0x30
+;   slli t4, a2, 0x30
+;   srli t1, t4, 0x30
+;   beq a7, t1, 0xc
 ;   addi a0, zero, 1
 ;   j 8
 ;   mv a0, zero

cranelift/filetests/filetests/isa/riscv64/narrow-arithmetic.clif

@@ -59,15 +59,16 @@ block0(v0: i32, v1: i8):
 
 ; VCode:
 ; block0:
-;   sext.b a1,a1
-;   addw a0,a0,a1
+;   slli a1,a1,56
+;   srai a3,a1,56
+;   addw a0,a0,a3
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
 ;   slli a1, a1, 0x38
-;   srai a1, a1, 0x38
-;   addw a0, a0, a1
+;   srai a3, a1, 0x38
+;   addw a0, a0, a3
 ;   ret
 
 function %add64_32(i64, i32) -> i64 {
@@ -85,8 +86,7 @@ block0(v0: i64, v1: i32):
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   slli a1, a1, 0x20
-;   srai a1, a1, 0x20
+;   sext.w a1, a1
 ;   add a0, a0, a1
 ;   ret
 

cranelift/filetests/filetests/isa/riscv64/shift-rotate.clif

@@ -105,30 +105,31 @@ block0(v0: i32, v1: i32):
 
 ; VCode:
 ; block0:
-;   uext.w a0,a0
-;   andi a2,a1,31
-;   li a4,32
-;   sub a6,a4,a2
-;   srl t3,a0,a2
-;   sll t0,a0,a6
-;   select_reg t2,zero,t0##condition=(a2 eq zero)
-;   or a0,t3,t2
+;   slli a0,a0,32
+;   srli a2,a0,32
+;   andi a4,a1,31
+;   li a6,32
+;   sub t3,a6,a4
+;   srl t0,a2,a4
+;   sll t2,a2,t3
+;   select_reg a1,zero,t2##condition=(a4 eq zero)
+;   or a0,t0,a1
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
 ;   slli a0, a0, 0x20
-;   srli a0, a0, 0x20
-;   andi a2, a1, 0x1f
-;   addi a4, zero, 0x20
-;   sub a6, a4, a2
-;   srl t3, a0, a2
-;   sll t0, a0, a6
-;   beqz a2, 0xc
-;   ori t2, t0, 0
+;   srli a2, a0, 0x20
+;   andi a4, a1, 0x1f
+;   addi a6, zero, 0x20
+;   sub t3, a6, a4
+;   srl t0, a2, a4
+;   sll t2, a2, t3
+;   beqz a4, 0xc
+;   ori a1, t2, 0
 ;   j 8
-;   ori t2, zero, 0
-;   or a0, t3, t2
+;   ori a1, zero, 0
+;   or a0, t0, a1
 ;   ret
 
 function %f2(i16, i16) -> i16 {
@@ -139,30 +140,31 @@ block0(v0: i16, v1: i16):
 
 ; VCode:
 ; block0:
-;   uext.h a0,a0
-;   andi a2,a1,15
-;   li a4,16
-;   sub a6,a4,a2
-;   srl t3,a0,a2
-;   sll t0,a0,a6
-;   select_reg t2,zero,t0##condition=(a2 eq zero)
-;   or a0,t3,t2
+;   slli a0,a0,48
+;   srli a2,a0,48
+;   andi a4,a1,15
+;   li a6,16
+;   sub t3,a6,a4
+;   srl t0,a2,a4
+;   sll t2,a2,t3
+;   select_reg a1,zero,t2##condition=(a4 eq zero)
+;   or a0,t0,a1
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
 ;   slli a0, a0, 0x30
-;   srli a0, a0, 0x30
-;   andi a2, a1, 0xf
-;   addi a4, zero, 0x10
-;   sub a6, a4, a2
-;   srl t3, a0, a2
-;   sll t0, a0, a6
-;   beqz a2, 0xc
-;   ori t2, t0, 0
+;   srli a2, a0, 0x30
+;   andi a4, a1, 0xf
+;   addi a6, zero, 0x10
+;   sub t3, a6, a4
+;   srl t0, a2, a4
+;   sll t2, a2, t3
+;   beqz a4, 0xc
+;   ori a1, t2, 0
 ;   j 8
-;   ori t2, zero, 0
-;   or a0, t3, t2
+;   ori a1, zero, 0
+;   or a0, t0, a1
 ;   ret
 
 function %f3(i8, i8) -> i8 {
@@ -173,7 +175,7 @@ block0(v0: i8, v1: i8):
 
 ; VCode:
 ; block0:
-;   uext.b a0,a0
+;   andi a0,a0,255
 ;   andi a2,a1,7
 ;   li a4,8
 ;   sub a6,a4,a2
@@ -297,30 +299,31 @@ block0(v0: i32, v1: i32):
 
 ; VCode:
 ; block0:
-;   uext.w a0,a0
-;   andi a2,a1,31
-;   li a4,32
-;   sub a6,a4,a2
-;   sll t3,a0,a2
-;   srl t0,a0,a6
-;   select_reg t2,zero,t0##condition=(a2 eq zero)
-;   or a0,t3,t2
+;   slli a0,a0,32
+;   srli a2,a0,32
+;   andi a4,a1,31
+;   li a6,32
+;   sub t3,a6,a4
+;   sll t0,a2,a4
+;   srl t2,a2,t3
+;   select_reg a1,zero,t2##condition=(a4 eq zero)
+;   or a0,t0,a1
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
 ;   slli a0, a0, 0x20
-;   srli a0, a0, 0x20
-;   andi a2, a1, 0x1f
-;   addi a4, zero, 0x20
-;   sub a6, a4, a2
-;   sll t3, a0, a2
-;   srl t0, a0, a6
-;   beqz a2, 0xc
-;   ori t2, t0, 0
+;   srli a2, a0, 0x20
+;   andi a4, a1, 0x1f
+;   addi a6, zero, 0x20
+;   sub t3, a6, a4
+;   sll t0, a2, a4
+;   srl t2, a2, t3
+;   beqz a4, 0xc
+;   ori a1, t2, 0
 ;   j 8
-;   ori t2, zero, 0
-;   or a0, t3, t2
+;   ori a1, zero, 0
+;   or a0, t0, a1
 ;   ret
 
 function %f6(i16, i16) -> i16 {
@@ -331,30 +334,31 @@ block0(v0: i16, v1: i16):
 
 ; VCode:
 ; block0:
-;   uext.h a0,a0
-;   andi a2,a1,15
-;   li a4,16
-;   sub a6,a4,a2
-;   sll t3,a0,a2
-;   srl t0,a0,a6
-;   select_reg t2,zero,t0##condition=(a2 eq zero)
-;   or a0,t3,t2
+;   slli a0,a0,48
+;   srli a2,a0,48
+;   andi a4,a1,15
+;   li a6,16
+;   sub t3,a6,a4
+;   sll t0,a2,a4
+;   srl t2,a2,t3
+;   select_reg a1,zero,t2##condition=(a4 eq zero)
+;   or a0,t0,a1
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
 ;   slli a0, a0, 0x30
-;   srli a0, a0, 0x30
-;   andi a2, a1, 0xf
-;   addi a4, zero, 0x10
-;   sub a6, a4, a2
-;   sll t3, a0, a2
-;   srl t0, a0, a6
-;   beqz a2, 0xc
-;   ori t2, t0, 0
+;   srli a2, a0, 0x30
+;   andi a4, a1, 0xf
+;   addi a6, zero, 0x10
+;   sub t3, a6, a4
+;   sll t0, a2, a4
+;   srl t2, a2, t3
+;   beqz a4, 0xc
+;   ori a1, t2, 0
 ;   j 8
-;   ori t2, zero, 0
-;   or a0, t3, t2
+;   ori a1, zero, 0
+;   or a0, t0, a1
 ;   ret
 
 function %f7(i8, i8) -> i8 {
@@ -365,7 +369,7 @@ block0(v0: i8, v1: i8):
 
 ; VCode:
 ; block0:
-;   uext.b a0,a0
+;   andi a0,a0,255
 ;   andi a2,a1,7
 ;   li a4,8
 ;   sub a6,a4,a2
@@ -430,17 +434,18 @@ block0(v0: i16, v1: i16):
 
 ; VCode:
 ; block0:
-;   uext.h a0,a0
-;   andi a2,a1,15
-;   srlw a0,a0,a2
+;   slli a0,a0,48
+;   srli a2,a0,48
+;   andi a4,a1,15
+;   srlw a0,a2,a4
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
 ;   slli a0, a0, 0x30
-;   srli a0, a0, 0x30
-;   andi a2, a1, 0xf
-;   srlw a0, a0, a2
+;   srli a2, a0, 0x30
+;   andi a4, a1, 0xf
+;   srlw a0, a2, a4
 ;   ret
 
 function %f11(i8, i8) -> i8 {
@@ -451,7 +456,7 @@ block0(v0: i8, v1: i8):
 
 ; VCode:
 ; block0:
-;   uext.b a0,a0
+;   andi a0,a0,255
 ;   andi a2,a1,7
 ;   srlw a0,a0,a2
 ;   ret
@@ -571,17 +576,18 @@ block0(v0: i16, v1: i16):
 
 ; VCode:
 ; block0:
-;   sext.h a0,a0
-;   andi a2,a1,15
-;   sra a0,a0,a2
+;   slli a0,a0,48
+;   srai a2,a0,48
+;   andi a4,a1,15
+;   sra a0,a2,a4
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
 ;   slli a0, a0, 0x30
-;   srai a0, a0, 0x30
-;   andi a2, a1, 0xf
-;   sra a0, a0, a2
+;   srai a2, a0, 0x30
+;   andi a4, a1, 0xf
+;   sra a0, a2, a4
 ;   ret
 
 function %f19(i8, i8) -> i8 {
@@ -592,17 +598,18 @@ block0(v0: i8, v1: i8):
 
 ; VCode:
 ; block0:
-;   sext.b a0,a0
-;   andi a2,a1,7
-;   sra a0,a0,a2
+;   slli a0,a0,56
+;   srai a2,a0,56
+;   andi a4,a1,7
+;   sra a0,a2,a4
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
 ;   slli a0, a0, 0x38
-;   srai a0, a0, 0x38
-;   andi a2, a1, 7
-;   sra a0, a0, a2
+;   srai a2, a0, 0x38
+;   andi a4, a1, 7
+;   sra a0, a2, a4
 ;   ret
 
 function %f20(i64) -> i64 {
@@ -682,32 +689,33 @@ block0(v0: i32):
 
 ; VCode:
 ; block0:
-;   uext.w t2,a0
-;   li a1,17
-;   andi a3,a1,31
-;   li a5,32
-;   sub a7,a5,a3
-;   sll t4,t2,a3
-;   srl t1,t2,a7
-;   select_reg a0,zero,t1##condition=(a3 eq zero)
-;   or a0,t4,a0
+;   slli t2,a0,32
+;   srli a1,t2,32
+;   li a3,17
+;   andi a5,a3,31
+;   li a7,32
+;   sub t4,a7,a5
+;   sll t1,a1,a5
+;   srl a0,a1,t4
+;   select_reg a2,zero,a0##condition=(a5 eq zero)
+;   or a0,t1,a2
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
 ;   slli t2, a0, 0x20
-;   srli t2, t2, 0x20
-;   addi a1, zero, 0x11
-;   andi a3, a1, 0x1f
-;   addi a5, zero, 0x20
-;   sub a7, a5, a3
-;   sll t4, t2, a3
-;   srl t1, t2, a7
-;   beqz a3, 0xc
-;   ori a0, t1, 0
+;   srli a1, t2, 0x20
+;   addi a3, zero, 0x11
+;   andi a5, a3, 0x1f
+;   addi a7, zero, 0x20
+;   sub t4, a7, a5
+;   sll t1, a1, a5
+;   srl a0, a1, t4
+;   beqz a5, 0xc
+;   ori a2, a0, 0
 ;   j 8
-;   ori a0, zero, 0
-;   or a0, t4, a0
+;   ori a2, zero, 0
+;   or a0, t1, a2
 ;   ret
 
 function %f23(i16) -> i16 {
@@ -719,32 +727,33 @@ block0(v0: i16):
 
 ; VCode:
 ; block0:
-;   uext.h t2,a0
-;   li a1,10
-;   andi a3,a1,15
-;   li a5,16
-;   sub a7,a5,a3
-;   sll t4,t2,a3
-;   srl t1,t2,a7
-;   select_reg a0,zero,t1##condition=(a3 eq zero)
-;   or a0,t4,a0
+;   slli t2,a0,48
+;   srli a1,t2,48
+;   li a3,10
+;   andi a5,a3,15
+;   li a7,16
+;   sub t4,a7,a5
+;   sll t1,a1,a5
+;   srl a0,a1,t4
+;   select_reg a2,zero,a0##condition=(a5 eq zero)
+;   or a0,t1,a2
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
 ;   slli t2, a0, 0x30
-;   srli t2, t2, 0x30
-;   addi a1, zero, 0xa
-;   andi a3, a1, 0xf
-;   addi a5, zero, 0x10
-;   sub a7, a5, a3
-;   sll t4, t2, a3
-;   srl t1, t2, a7
-;   beqz a3, 0xc
-;   ori a0, t1, 0
+;   srli a1, t2, 0x30
+;   addi a3, zero, 0xa
+;   andi a5, a3, 0xf
+;   addi a7, zero, 0x10
+;   sub t4, a7, a5
+;   sll t1, a1, a5
+;   srl a0, a1, t4
+;   beqz a5, 0xc
+;   ori a2, a0, 0
 ;   j 8
-;   ori a0, zero, 0
-;   or a0, t4, a0
+;   ori a2, zero, 0
+;   or a0, t1, a2
 ;   ret
 
 function %f24(i8) -> i8 {
@@ -756,7 +765,7 @@ block0(v0: i8):
 
 ; VCode:
 ; block0:
-;   uext.b t2,a0
+;   andi t2,a0,255
 ;   li a1,3
 ;   andi a3,a1,7
 ;   li a5,8

cranelift/filetests/filetests/isa/riscv64/uadd_overflow_trap.clif

@@ -11,23 +11,25 @@ block0(v0: i32):
 ; VCode:
 ; block0:
 ;   li t2,127
-;   uext.w a1,a0
-;   uext.w a3,t2
-;   add a0,a1,a3
-;   srli a7,a0,32
-;   trap_if a7,user0
+;   slli a1,a0,32
+;   srli a3,a1,32
+;   slli a5,t2,32
+;   srli a7,a5,32
+;   add a0,a3,a7
+;   srli t1,a0,32
+;   trap_if t1,user0
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
 ;   addi t2, zero, 0x7f
 ;   slli a1, a0, 0x20
-;   srli a1, a1, 0x20
-;   slli a3, t2, 0x20
-;   srli a3, a3, 0x20
-;   add a0, a1, a3
-;   srli a7, a0, 0x20
-;   beqz a7, 8
+;   srli a3, a1, 0x20
+;   slli a5, t2, 0x20
+;   srli a7, a5, 0x20
+;   add a0, a3, a7
+;   srli t1, a0, 0x20
+;   beqz t1, 8
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: user0
 ;   ret
 
@@ -41,23 +43,25 @@ block0(v0: i32):
 ; VCode:
 ; block0:
 ;   li t2,127
-;   uext.w a1,t2
-;   uext.w a3,a0
-;   add a0,a1,a3
-;   srli a7,a0,32
-;   trap_if a7,user0
+;   slli a1,t2,32
+;   srli a3,a1,32
+;   slli a5,a0,32
+;   srli a7,a5,32
+;   add a0,a3,a7
+;   srli t1,a0,32
+;   trap_if t1,user0
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
 ;   addi t2, zero, 0x7f
 ;   slli a1, t2, 0x20
-;   srli a1, a1, 0x20
-;   slli a3, a0, 0x20
-;   srli a3, a3, 0x20
-;   add a0, a1, a3
-;   srli a7, a0, 0x20
-;   beqz a7, 8
+;   srli a3, a1, 0x20
+;   slli a5, a0, 0x20
+;   srli a7, a5, 0x20
+;   add a0, a3, a7
+;   srli t1, a0, 0x20
+;   beqz t1, 8
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: user0
 ;   ret
 
@@ -69,22 +73,24 @@ block0(v0: i32, v1: i32):
 
 ; VCode:
 ; block0:
-;   uext.w a0,a0
-;   uext.w a2,a1
-;   add a0,a0,a2
-;   srli a6,a0,32
-;   trap_if a6,user0
+;   slli a0,a0,32
+;   srli a2,a0,32
+;   slli a4,a1,32
+;   srli a6,a4,32
+;   add a0,a2,a6
+;   srli t0,a0,32
+;   trap_if t0,user0
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
 ;   slli a0, a0, 0x20
-;   srli a0, a0, 0x20
-;   slli a2, a1, 0x20
-;   srli a2, a2, 0x20
-;   add a0, a0, a2
-;   srli a6, a0, 0x20
-;   beqz a6, 8
+;   srli a2, a0, 0x20
+;   slli a4, a1, 0x20
+;   srli a6, a4, 0x20
+;   add a0, a2, a6
+;   srli t0, a0, 0x20
+;   beqz t0, 8
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: user0
 ;   ret
 

cranelift/filetests/filetests/isa/riscv64/uextend-sextend.clif

@@ -1,205 +0,0 @@
-test compile precise-output
-set unwind_info=false
-target riscv64
-
-function %f_u_8_64(i8) -> i64 {
-block0(v0: i8):
-  v1 = uextend.i64 v0
-  return v1
-}
-
-; VCode:
-; block0:
-;   uext.b a0,a0
-;   ret
-; 
-; Disassembled:
-; block0: ; offset 0x0
-;   andi a0, a0, 0xff
-;   ret
-
-function %f_u_8_32(i8) -> i32 {
-block0(v0: i8):
-  v1 = uextend.i32 v0
-  return v1
-}
-
-; VCode:
-; block0:
-;   uext.b a0,a0
-;   ret
-; 
-; Disassembled:
-; block0: ; offset 0x0
-;   andi a0, a0, 0xff
-;   ret
-
-function %f_u_8_16(i8) -> i16 {
-block0(v0: i8):
-  v1 = uextend.i16 v0
-  return v1
-}
-
-; VCode:
-; block0:
-;   uext.b a0,a0
-;   ret
-; 
-; Disassembled:
-; block0: ; offset 0x0
-;   andi a0, a0, 0xff
-;   ret
-
-function %f_s_8_64(i8) -> i64 {
-block0(v0: i8):
-  v1 = sextend.i64 v0
-  return v1
-}
-
-; VCode:
-; block0:
-;   sext.b a0,a0
-;   ret
-; 
-; Disassembled:
-; block0: ; offset 0x0
-;   slli a0, a0, 0x38
-;   srai a0, a0, 0x38
-;   ret
-
-function %f_s_8_32(i8) -> i32 {
-block0(v0: i8):
-  v1 = sextend.i32 v0
-  return v1
-}
-
-; VCode:
-; block0:
-;   sext.b a0,a0
-;   ret
-; 
-; Disassembled:
-; block0: ; offset 0x0
-;   slli a0, a0, 0x38
-;   srai a0, a0, 0x38
-;   ret
-
-function %f_s_8_16(i8) -> i16 {
-block0(v0: i8):
-  v1 = sextend.i16 v0
-  return v1
-}
-
-; VCode:
-; block0:
-;   sext.b a0,a0
-;   ret
-; 
-; Disassembled:
-; block0: ; offset 0x0
-;   slli a0, a0, 0x38
-;   srai a0, a0, 0x38
-;   ret
-
-function %f_u_16_64(i16) -> i64 {
-block0(v0: i16):
-  v1 = uextend.i64 v0
-  return v1
-}
-
-; VCode:
-; block0:
-;   uext.h a0,a0
-;   ret
-; 
-; Disassembled:
-; block0: ; offset 0x0
-;   slli a0, a0, 0x30
-;   srli a0, a0, 0x30
-;   ret
-
-function %f_u_16_32(i16) -> i32 {
-block0(v0: i16):
-  v1 = uextend.i32 v0
-  return v1
-}
-
-; VCode:
-; block0:
-;   uext.h a0,a0
-;   ret
-; 
-; Disassembled:
-; block0: ; offset 0x0
-;   slli a0, a0, 0x30
-;   srli a0, a0, 0x30
-;   ret
-
-function %f_s_16_64(i16) -> i64 {
-block0(v0: i16):
-  v1 = sextend.i64 v0
-  return v1
-}
-
-; VCode:
-; block0:
-;   sext.h a0,a0
-;   ret
-; 
-; Disassembled:
-; block0: ; offset 0x0
-;   slli a0, a0, 0x30
-;   srai a0, a0, 0x30
-;   ret
-
-function %f_s_16_32(i16) -> i32 {
-block0(v0: i16):
-  v1 = sextend.i32 v0
-  return v1
-}
-
-; VCode:
-; block0:
-;   sext.h a0,a0
-;   ret
-; 
-; Disassembled:
-; block0: ; offset 0x0
-;   slli a0, a0, 0x30
-;   srai a0, a0, 0x30
-;   ret
-
-function %f_u_32_64(i32) -> i64 {
-block0(v0: i32):
-  v1 = uextend.i64 v0
-  return v1
-}
-
-; VCode:
-; block0:
-;   uext.w a0,a0
-;   ret
-; 
-; Disassembled:
-; block0: ; offset 0x0
-;   slli a0, a0, 0x20
-;   srli a0, a0, 0x20
-;   ret
-
-function %f_s_32_64(i32) -> i64 {
-block0(v0: i32):
-  v1 = sextend.i64 v0
-  return v1
-}
-
-; VCode:
-; block0:
-;   sext.w a0,a0
-;   ret
-; 
-; Disassembled:
-; block0: ; offset 0x0
-;   slli a0, a0, 0x20
-;   srai a0, a0, 0x20
-;   ret
-

cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i32_access_0_offset.wat

@@ -41,15 +41,16 @@
 
 ;; function u0:0:
 ;; block0:
-;;   uext.w a6,a0
+;;   slli a6,a0,32
+;;   srli t3,a6,32
 ;;   ld a7,8(a2)
 ;;   addi a7,a7,-4
-;;   ugt a7,a6,a7##ty=i64
+;;   ugt a7,t3,a7##ty=i64
 ;;   bne a7,zero,taken(label1),not_taken(label2)
 ;; block2:
-;;   ld t3,0(a2)
-;;   add t3,t3,a6
-;;   sw a1,0(t3)
+;;   ld t4,0(a2)
+;;   add t4,t4,t3
+;;   sw a1,0(t4)
 ;;   j label3
 ;; block3:
 ;;   ret
@@ -58,15 +59,16 @@
 ;;
 ;; function u0:1:
 ;; block0:
-;;   uext.w a6,a0
+;;   slli a6,a0,32
+;;   srli t3,a6,32
 ;;   ld a7,8(a1)
 ;;   addi a7,a7,-4
-;;   ugt a7,a6,a7##ty=i64
+;;   ugt a7,t3,a7##ty=i64
 ;;   bne a7,zero,taken(label1),not_taken(label2)
 ;; block2:
-;;   ld t3,0(a1)
-;;   add t3,t3,a6
-;;   lw a0,0(t3)
+;;   ld t4,0(a1)
+;;   add t4,t4,t3
+;;   lw a0,0(t4)
 ;;   j label3
 ;; block3:
 ;;   ret

cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i32_access_0x1000_offset.wat

@@ -41,19 +41,20 @@
 
 ;; function u0:0:
 ;; block0:
-;;   uext.w t0,a0
+;;   slli t0,a0,32
+;;   srli t2,t0,32
 ;;   ld t1,8(a2)
-;;   lui t4,1048575
-;;   addi t4,t4,4092
-;;   add t2,t1,t4
-;;   ugt t1,t0,t2##ty=i64
+;;   lui t0,1048575
+;;   addi t0,t0,4092
+;;   add a0,t1,t0
+;;   ugt t1,t2,a0##ty=i64
 ;;   bne t1,zero,taken(label1),not_taken(label2)
 ;; block2:
-;;   ld t2,0(a2)
-;;   add t2,t2,t0
-;;   lui t1,1
-;;   add a0,t2,t1
-;;   sw a1,0(a0)
+;;   ld a0,0(a2)
+;;   add a0,a0,t2
+;;   lui t2,1
+;;   add a2,a0,t2
+;;   sw a1,0(a2)
 ;;   j label3
 ;; block3:
 ;;   ret
@@ -62,19 +63,20 @@
 ;;
 ;; function u0:1:
 ;; block0:
-;;   uext.w t0,a0
+;;   slli t0,a0,32
+;;   srli t2,t0,32
 ;;   ld t1,8(a1)
-;;   lui t4,1048575
-;;   addi t4,t4,4092
-;;   add t2,t1,t4
-;;   ugt t1,t0,t2##ty=i64
+;;   lui t0,1048575
+;;   addi t0,t0,4092
+;;   add a0,t1,t0
+;;   ugt t1,t2,a0##ty=i64
 ;;   bne t1,zero,taken(label1),not_taken(label2)
 ;; block2:
-;;   ld t2,0(a1)
-;;   add t2,t2,t0
-;;   lui t1,1
-;;   add a0,t2,t1
-;;   lw a0,0(a0)
+;;   ld a0,0(a1)
+;;   add a0,a0,t2
+;;   lui t2,1
+;;   add a1,a0,t2
+;;   lw a0,0(a1)
 ;;   j label3
 ;; block3:
 ;;   ret

cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i32_access_0xffff0000_offset.wat

@@ -41,19 +41,20 @@
 
 ;; function u0:0:
 ;; block0:
-;;   uext.w t0,a0
-;;   auipc t3,0; ld t3,12(t3); j 12; .8byte 0xffff0004
-;;   add t1,t0,t3
-;;   ult t2,t1,t0##ty=i64
-;;   trap_if t2,heap_oob
-;;   ld t2,8(a2)
-;;   ugt t1,t1,t2##ty=i64
-;;   bne t1,zero,taken(label1),not_taken(label2)
+;;   slli t0,a0,32
+;;   srli t2,t0,32
+;;   auipc t4,0; ld t4,12(t4); j 12; .8byte 0xffff0004
+;;   add t1,t2,t4
+;;   ult a0,t1,t2##ty=i64
+;;   trap_if a0,heap_oob
+;;   ld a0,8(a2)
+;;   ugt a0,t1,a0##ty=i64
+;;   bne a0,zero,taken(label1),not_taken(label2)
 ;; block2:
-;;   ld a0,0(a2)
-;;   add a0,a0,t0
-;;   auipc t2,0; ld t2,12(t2); j 12; .8byte 0xffff0000
-;;   add a2,a0,t2
+;;   ld a2,0(a2)
+;;   add a2,a2,t2
+;;   auipc a0,0; ld a0,12(a0); j 12; .8byte 0xffff0000
+;;   add a2,a2,a0
 ;;   sw a1,0(a2)
 ;;   j label3
 ;; block3:
@@ -63,20 +64,21 @@
 ;;
 ;; function u0:1:
 ;; block0:
-;;   uext.w t0,a0
-;;   auipc t3,0; ld t3,12(t3); j 12; .8byte 0xffff0004
-;;   add t1,t0,t3
-;;   ult t2,t1,t0##ty=i64
-;;   trap_if t2,heap_oob
-;;   ld t2,8(a1)
-;;   ugt t1,t1,t2##ty=i64
-;;   bne t1,zero,taken(label1),not_taken(label2)
+;;   slli t0,a0,32
+;;   srli t2,t0,32
+;;   auipc t4,0; ld t4,12(t4); j 12; .8byte 0xffff0004
+;;   add t1,t2,t4
+;;   ult a0,t1,t2##ty=i64
+;;   trap_if a0,heap_oob
+;;   ld a0,8(a1)
+;;   ugt a0,t1,a0##ty=i64
+;;   bne a0,zero,taken(label1),not_taken(label2)
 ;; block2:
-;;   ld a0,0(a1)
-;;   add a0,a0,t0
-;;   auipc t2,0; ld t2,12(t2); j 12; .8byte 0xffff0000
-;;   add a1,a0,t2
-;;   lw a0,0(a1)
+;;   ld a1,0(a1)
+;;   add a1,a1,t2
+;;   auipc a0,0; ld a0,12(a0); j 12; .8byte 0xffff0000
+;;   add a2,a1,a0
+;;   lw a0,0(a2)
 ;;   j label3
 ;; block3:
 ;;   ret

cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i8_access_0_offset.wat

@@ -41,14 +41,15 @@
 
 ;; function u0:0:
 ;; block0:
-;;   uext.w a5,a0
+;;   slli a5,a0,32
+;;   srli a7,a5,32
 ;;   ld a6,8(a2)
-;;   uge a6,a5,a6##ty=i64
+;;   uge a6,a7,a6##ty=i64
 ;;   bne a6,zero,taken(label1),not_taken(label2)
 ;; block2:
-;;   ld a7,0(a2)
-;;   add a7,a7,a5
-;;   sb a1,0(a7)
+;;   ld t3,0(a2)
+;;   add t3,t3,a7
+;;   sb a1,0(t3)
 ;;   j label3
 ;; block3:
 ;;   ret
@@ -57,14 +58,15 @@
 ;;
 ;; function u0:1:
 ;; block0:
-;;   uext.w a5,a0
+;;   slli a5,a0,32
+;;   srli a7,a5,32
 ;;   ld a6,8(a1)
-;;   uge a6,a5,a6##ty=i64
+;;   uge a6,a7,a6##ty=i64
 ;;   bne a6,zero,taken(label1),not_taken(label2)
 ;; block2:
-;;   ld a7,0(a1)
-;;   add a7,a7,a5
-;;   lbu a0,0(a7)
+;;   ld t3,0(a1)
+;;   add t3,t3,a7
+;;   lbu a0,0(t3)
 ;;   j label3
 ;; block3:
 ;;   ret

cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i8_access_0x1000_offset.wat

@@ -41,19 +41,20 @@
 
 ;; function u0:0:
 ;; block0:
-;;   uext.w t0,a0
+;;   slli t0,a0,32
+;;   srli t2,t0,32
 ;;   ld t1,8(a2)
-;;   lui t4,1048575
-;;   addi t4,t4,4095
-;;   add t2,t1,t4
-;;   ugt t1,t0,t2##ty=i64
+;;   lui t0,1048575
+;;   addi t0,t0,4095
+;;   add a0,t1,t0
+;;   ugt t1,t2,a0##ty=i64
 ;;   bne t1,zero,taken(label1),not_taken(label2)
 ;; block2:
-;;   ld t2,0(a2)
-;;   add t2,t2,t0
-;;   lui t1,1
-;;   add a0,t2,t1
-;;   sb a1,0(a0)
+;;   ld a0,0(a2)
+;;   add a0,a0,t2
+;;   lui t2,1
+;;   add a2,a0,t2
+;;   sb a1,0(a2)
 ;;   j label3
 ;; block3:
 ;;   ret
@@ -62,19 +63,20 @@
 ;;
 ;; function u0:1:
 ;; block0:
-;;   uext.w t0,a0
+;;   slli t0,a0,32
+;;   srli t2,t0,32
 ;;   ld t1,8(a1)
-;;   lui t4,1048575
-;;   addi t4,t4,4095
-;;   add t2,t1,t4
-;;   ugt t1,t0,t2##ty=i64
+;;   lui t0,1048575
+;;   addi t0,t0,4095
+;;   add a0,t1,t0
+;;   ugt t1,t2,a0##ty=i64
 ;;   bne t1,zero,taken(label1),not_taken(label2)
 ;; block2:
-;;   ld t2,0(a1)
-;;   add t2,t2,t0
-;;   lui t1,1
-;;   add a0,t2,t1
-;;   lbu a0,0(a0)
+;;   ld a0,0(a1)
+;;   add a0,a0,t2
+;;   lui t2,1
+;;   add a1,a0,t2
+;;   lbu a0,0(a1)
 ;;   j label3
 ;; block3:
 ;;   ret

cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat

@@ -41,19 +41,20 @@
 
 ;; function u0:0:
 ;; block0:
-;;   uext.w t0,a0
-;;   auipc t3,0; ld t3,12(t3); j 12; .8byte 0xffff0001
-;;   add t1,t0,t3
-;;   ult t2,t1,t0##ty=i64
-;;   trap_if t2,heap_oob
-;;   ld t2,8(a2)
-;;   ugt t1,t1,t2##ty=i64
-;;   bne t1,zero,taken(label1),not_taken(label2)
+;;   slli t0,a0,32
+;;   srli t2,t0,32
+;;   auipc t4,0; ld t4,12(t4); j 12; .8byte 0xffff0001
+;;   add t1,t2,t4
+;;   ult a0,t1,t2##ty=i64
+;;   trap_if a0,heap_oob
+;;   ld a0,8(a2)
+;;   ugt a0,t1,a0##ty=i64
+;;   bne a0,zero,taken(label1),not_taken(label2)
 ;; block2:
-;;   ld a0,0(a2)
-;;   add a0,a0,t0
-;;   auipc t2,0; ld t2,12(t2); j 12; .8byte 0xffff0000
-;;   add a2,a0,t2
+;;   ld a2,0(a2)
+;;   add a2,a2,t2
+;;   auipc a0,0; ld a0,12(a0); j 12; .8byte 0xffff0000
+;;   add a2,a2,a0
 ;;   sb a1,0(a2)
 ;;   j label3
 ;; block3:
@@ -63,20 +64,21 @@
 ;;
 ;; function u0:1:
 ;; block0:
-;;   uext.w t0,a0
-;;   auipc t3,0; ld t3,12(t3); j 12; .8byte 0xffff0001
-;;   add t1,t0,t3
-;;   ult t2,t1,t0##ty=i64
-;;   trap_if t2,heap_oob
-;;   ld t2,8(a1)
-;;   ugt t1,t1,t2##ty=i64
-;;   bne t1,zero,taken(label1),not_taken(label2)
+;;   slli t0,a0,32
+;;   srli t2,t0,32
+;;   auipc t4,0; ld t4,12(t4); j 12; .8byte 0xffff0001
+;;   add t1,t2,t4
+;;   ult a0,t1,t2##ty=i64
+;;   trap_if a0,heap_oob
+;;   ld a0,8(a1)
+;;   ugt a0,t1,a0##ty=i64
+;;   bne a0,zero,taken(label1),not_taken(label2)
 ;; block2:
-;;   ld a0,0(a1)
-;;   add a0,a0,t0
-;;   auipc t2,0; ld t2,12(t2); j 12; .8byte 0xffff0000
-;;   add a1,a0,t2
-;;   lbu a0,0(a1)
+;;   ld a1,0(a1)
+;;   add a1,a1,t2
+;;   auipc a0,0; ld a0,12(a0); j 12; .8byte 0xffff0000
+;;   add a2,a1,a0
+;;   lbu a0,0(a2)
 ;;   j label3
 ;; block3:
 ;;   ret

cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i32_access_0_offset.wat

@@ -41,30 +41,32 @@
 
 ;; function u0:0:
 ;; block0:
-;;   uext.w t3,a0
+;;   slli t3,a0,32
+;;   srli t0,t3,32
 ;;   ld t4,8(a2)
 ;;   addi t4,t4,-4
-;;   ld t0,0(a2)
-;;   add t0,t0,t3
-;;   ugt a7,t3,t4##ty=i64
-;;   li t4,0
-;;   selectif_spectre_guard t3,t4,t0##test=a7
-;;   sw a1,0(t3)
+;;   ld t1,0(a2)
+;;   add t1,t1,t0
+;;   ugt t3,t0,t4##ty=i64
+;;   li t0,0
+;;   selectif_spectre_guard t4,t0,t1##test=t3
+;;   sw a1,0(t4)
 ;;   j label1
 ;; block1:
 ;;   ret
 ;;
 ;; function u0:1:
 ;; block0:
-;;   uext.w t3,a0
+;;   slli t3,a0,32
+;;   srli t0,t3,32
 ;;   ld t4,8(a1)
 ;;   addi t4,t4,-4
-;;   ld t0,0(a1)
-;;   add t0,t0,t3
-;;   ugt a7,t3,t4##ty=i64
-;;   li t4,0
-;;   selectif_spectre_guard t3,t4,t0##test=a7
-;;   lw a0,0(t3)
+;;   ld t1,0(a1)
+;;   add t1,t1,t0
+;;   ugt t3,t0,t4##ty=i64
+;;   li t0,0
+;;   selectif_spectre_guard t4,t0,t1##test=t3
+;;   lw a0,0(t4)
 ;;   j label1
 ;; block1:
 ;;   ret

cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i32_access_0x1000_offset.wat

@@ -41,38 +41,40 @@
 
 ;; function u0:0:
 ;; block0:
-;;   uext.w t2,a0
+;;   slli t2,a0,32
+;;   srli a3,t2,32
 ;;   ld a0,8(a2)
-;;   lui t1,1048575
-;;   addi t1,t1,4092
-;;   add a3,a0,t1
+;;   lui t2,1048575
+;;   addi t2,t2,4092
+;;   add a4,a0,t2
 ;;   ld a0,0(a2)
-;;   add a0,a0,t2
-;;   lui t1,1
-;;   add a0,a0,t1
-;;   ugt t1,t2,a3##ty=i64
-;;   li a2,0
-;;   selectif_spectre_guard t2,a2,a0##test=t1
-;;   sw a1,0(t2)
+;;   add a0,a0,a3
+;;   lui t2,1
+;;   add a2,a0,t2
+;;   ugt t2,a3,a4##ty=i64
+;;   li a3,0
+;;   selectif_spectre_guard a0,a3,a2##test=t2
+;;   sw a1,0(a0)
 ;;   j label1
 ;; block1:
 ;;   ret
 ;;
 ;; function u0:1:
 ;; block0:
-;;   uext.w t2,a0
+;;   slli t2,a0,32
+;;   srli a2,t2,32
 ;;   ld a0,8(a1)
-;;   lui t1,1048575
-;;   addi t1,t1,4092
-;;   add a2,a0,t1
+;;   lui t2,1048575
+;;   addi t2,t2,4092
+;;   add a3,a0,t2
 ;;   ld a0,0(a1)
-;;   add a0,a0,t2
-;;   lui t1,1
-;;   add a0,a0,t1
-;;   ugt t1,t2,a2##ty=i64
-;;   li a1,0
-;;   selectif_spectre_guard t2,a1,a0##test=t1
-;;   lw a0,0(t2)
+;;   add a0,a0,a2
+;;   lui t2,1
+;;   add a1,a0,t2
+;;   ugt t2,a2,a3##ty=i64
+;;   li a2,0
+;;   selectif_spectre_guard a0,a2,a1##test=t2
+;;   lw a0,0(a0)
 ;;   j label1
 ;; block1:
 ;;   ret

cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i32_access_0xffff0000_offset.wat

@@ -41,40 +41,42 @@
 
 ;; function u0:0:
 ;; block0:
-;;   uext.w a0,a0
-;;   auipc t0,0; ld t0,12(t0); j 12; .8byte 0xffff0004
-;;   add t2,a0,t0
-;;   ult a3,t2,a0##ty=i64
-;;   trap_if a3,heap_oob
-;;   ld a3,8(a2)
+;;   slli t2,a0,32
+;;   srli a3,t2,32
+;;   auipc t1,0; ld t1,12(t1); j 12; .8byte 0xffff0004
+;;   add a0,a3,t1
+;;   ult a4,a0,a3##ty=i64
+;;   trap_if a4,heap_oob
+;;   ld a4,8(a2)
 ;;   ld a2,0(a2)
-;;   add a0,a2,a0
-;;   auipc a2,0; ld a2,12(a2); j 12; .8byte 0xffff0000
-;;   add a2,a0,a2
-;;   ugt t2,t2,a3##ty=i64
+;;   add a2,a2,a3
+;;   auipc a3,0; ld a3,12(a3); j 12; .8byte 0xffff0000
+;;   add a2,a2,a3
+;;   ugt a0,a0,a4##ty=i64
 ;;   li a3,0
-;;   selectif_spectre_guard a0,a3,a2##test=t2
-;;   sw a1,0(a0)
+;;   selectif_spectre_guard a4,a3,a2##test=a0
+;;   sw a1,0(a4)
 ;;   j label1
 ;; block1:
 ;;   ret
 ;;
 ;; function u0:1:
 ;; block0:
-;;   uext.w a0,a0
-;;   auipc t0,0; ld t0,12(t0); j 12; .8byte 0xffff0004
-;;   add t2,a0,t0
-;;   ult a2,t2,a0##ty=i64
-;;   trap_if a2,heap_oob
-;;   ld a2,8(a1)
+;;   slli t2,a0,32
+;;   srli a2,t2,32
+;;   auipc t1,0; ld t1,12(t1); j 12; .8byte 0xffff0004
+;;   add a0,a2,t1
+;;   ult a3,a0,a2##ty=i64
+;;   trap_if a3,heap_oob
+;;   ld a3,8(a1)
 ;;   ld a1,0(a1)
-;;   add a0,a1,a0
-;;   auipc a1,0; ld a1,12(a1); j 12; .8byte 0xffff0000
-;;   add a1,a0,a1
-;;   ugt t2,t2,a2##ty=i64
-;;   li a2,0
-;;   selectif_spectre_guard a0,a2,a1##test=t2
-;;   lw a0,0(a0)
+;;   add a1,a1,a2
+;;   auipc a2,0; ld a2,12(a2); j 12; .8byte 0xffff0000
+;;   add a2,a1,a2
+;;   ugt a0,a0,a3##ty=i64
+;;   li a3,0
+;;   selectif_spectre_guard a1,a3,a2##test=a0
+;;   lw a0,0(a1)
 ;;   j label1
 ;; block1:
 ;;   ret

cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0_offset.wat

@@ -41,28 +41,30 @@
 
 ;; function u0:0:
 ;; block0:
-;;   uext.w a7,a0
+;;   slli a7,a0,32
+;;   srli t4,a7,32
 ;;   ld t3,8(a2)
-;;   ld t4,0(a2)
-;;   add t4,t4,a7
-;;   uge a6,a7,t3##ty=i64
-;;   li t3,0
-;;   selectif_spectre_guard a7,t3,t4##test=a6
-;;   sb a1,0(a7)
+;;   ld t0,0(a2)
+;;   add t0,t0,t4
+;;   uge a7,t4,t3##ty=i64
+;;   li t4,0
+;;   selectif_spectre_guard t3,t4,t0##test=a7
+;;   sb a1,0(t3)
 ;;   j label1
 ;; block1:
 ;;   ret
 ;;
 ;; function u0:1:
 ;; block0:
-;;   uext.w a7,a0
+;;   slli a7,a0,32
+;;   srli t4,a7,32
 ;;   ld t3,8(a1)
-;;   ld t4,0(a1)
-;;   add t4,t4,a7
-;;   uge a6,a7,t3##ty=i64
-;;   li t3,0
-;;   selectif_spectre_guard a7,t3,t4##test=a6
-;;   lbu a0,0(a7)
+;;   ld t0,0(a1)
+;;   add t0,t0,t4
+;;   uge a7,t4,t3##ty=i64
+;;   li t4,0
+;;   selectif_spectre_guard t3,t4,t0##test=a7
+;;   lbu a0,0(t3)
 ;;   j label1
 ;; block1:
 ;;   ret

cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat

@@ -41,38 +41,40 @@
 
 ;; function u0:0:
 ;; block0:
-;;   uext.w t2,a0
+;;   slli t2,a0,32
+;;   srli a3,t2,32
 ;;   ld a0,8(a2)
-;;   lui t1,1048575
-;;   addi t1,t1,4095
-;;   add a3,a0,t1
+;;   lui t2,1048575
+;;   addi t2,t2,4095
+;;   add a4,a0,t2
 ;;   ld a0,0(a2)
-;;   add a0,a0,t2
-;;   lui t1,1
-;;   add a0,a0,t1
-;;   ugt t1,t2,a3##ty=i64
-;;   li a2,0
-;;   selectif_spectre_guard t2,a2,a0##test=t1
-;;   sb a1,0(t2)
+;;   add a0,a0,a3
+;;   lui t2,1
+;;   add a2,a0,t2
+;;   ugt t2,a3,a4##ty=i64
+;;   li a3,0
+;;   selectif_spectre_guard a0,a3,a2##test=t2
+;;   sb a1,0(a0)
 ;;   j label1
 ;; block1:
 ;;   ret
 ;;
 ;; function u0:1:
 ;; block0:
-;;   uext.w t2,a0
+;;   slli t2,a0,32
+;;   srli a2,t2,32
 ;;   ld a0,8(a1)
-;;   lui t1,1048575
-;;   addi t1,t1,4095
-;;   add a2,a0,t1
+;;   lui t2,1048575
+;;   addi t2,t2,4095
+;;   add a3,a0,t2
 ;;   ld a0,0(a1)
-;;   add a0,a0,t2
-;;   lui t1,1
-;;   add a0,a0,t1
-;;   ugt t1,t2,a2##ty=i64
-;;   li a1,0
-;;   selectif_spectre_guard t2,a1,a0##test=t1
-;;   lbu a0,0(t2)
+;;   add a0,a0,a2
+;;   lui t2,1
+;;   add a1,a0,t2
+;;   ugt t2,a2,a3##ty=i64
+;;   li a2,0
+;;   selectif_spectre_guard a0,a2,a1##test=t2
+;;   lbu a0,0(a0)
 ;;   j label1
 ;; block1:
 ;;   ret

cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat

@@ -41,40 +41,42 @@
 
 ;; function u0:0:
 ;; block0:
-;;   uext.w a0,a0
-;;   auipc t0,0; ld t0,12(t0); j 12; .8byte 0xffff0001
-;;   add t2,a0,t0
-;;   ult a3,t2,a0##ty=i64
-;;   trap_if a3,heap_oob
-;;   ld a3,8(a2)
+;;   slli t2,a0,32
+;;   srli a3,t2,32
+;;   auipc t1,0; ld t1,12(t1); j 12; .8byte 0xffff0001
+;;   add a0,a3,t1
+;;   ult a4,a0,a3##ty=i64
+;;   trap_if a4,heap_oob
+;;   ld a4,8(a2)
 ;;   ld a2,0(a2)
-;;   add a0,a2,a0
-;;   auipc a2,0; ld a2,12(a2); j 12; .8byte 0xffff0000
-;;   add a2,a0,a2
-;;   ugt t2,t2,a3##ty=i64
+;;   add a2,a2,a3
+;;   auipc a3,0; ld a3,12(a3); j 12; .8byte 0xffff0000
+;;   add a2,a2,a3
+;;   ugt a0,a0,a4##ty=i64
 ;;   li a3,0
-;;   selectif_spectre_guard a0,a3,a2##test=t2
-;;   sb a1,0(a0)
+;;   selectif_spectre_guard a4,a3,a2##test=a0
+;;   sb a1,0(a4)
 ;;   j label1
 ;; block1:
 ;;   ret
 ;;
 ;; function u0:1:
 ;; block0:
-;;   uext.w a0,a0
-;;   auipc t0,0; ld t0,12(t0); j 12; .8byte 0xffff0001
-;;   add t2,a0,t0
-;;   ult a2,t2,a0##ty=i64
-;;   trap_if a2,heap_oob
-;;   ld a2,8(a1)
+;;   slli t2,a0,32
+;;   srli a2,t2,32
+;;   auipc t1,0; ld t1,12(t1); j 12; .8byte 0xffff0001
+;;   add a0,a2,t1
+;;   ult a3,a0,a2##ty=i64
+;;   trap_if a3,heap_oob
+;;   ld a3,8(a1)
 ;;   ld a1,0(a1)
-;;   add a0,a1,a0
-;;   auipc a1,0; ld a1,12(a1); j 12; .8byte 0xffff0000
-;;   add a1,a0,a1
-;;   ugt t2,t2,a2##ty=i64
-;;   li a2,0
-;;   selectif_spectre_guard a0,a2,a1##test=t2
-;;   lbu a0,0(a0)
+;;   add a1,a1,a2
+;;   auipc a2,0; ld a2,12(a2); j 12; .8byte 0xffff0000
+;;   add a2,a1,a2
+;;   ugt a0,a0,a3##ty=i64
+;;   li a3,0
+;;   selectif_spectre_guard a1,a3,a2##test=a0
+;;   lbu a0,0(a1)
 ;;   j label1
 ;; block1:
 ;;   ret

cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i32_access_0_offset.wat

@@ -41,15 +41,16 @@
 
 ;; function u0:0:
 ;; block0:
-;;   uext.w a6,a0
+;;   slli a6,a0,32
+;;   srli t3,a6,32
 ;;   ld a7,8(a2)
 ;;   addi a7,a7,-4
-;;   ugt a7,a6,a7##ty=i64
+;;   ugt a7,t3,a7##ty=i64
 ;;   bne a7,zero,taken(label1),not_taken(label2)
 ;; block2:
-;;   ld t3,0(a2)
-;;   add t3,t3,a6
-;;   sw a1,0(t3)
+;;   ld t4,0(a2)
+;;   add t4,t4,t3
+;;   sw a1,0(t4)
 ;;   j label3
 ;; block3:
 ;;   ret
@@ -58,15 +59,16 @@
 ;;
 ;; function u0:1:
 ;; block0:
-;;   uext.w a6,a0
+;;   slli a6,a0,32
+;;   srli t3,a6,32
 ;;   ld a7,8(a1)
 ;;   addi a7,a7,-4
-;;   ugt a7,a6,a7##ty=i64
+;;   ugt a7,t3,a7##ty=i64
 ;;   bne a7,zero,taken(label1),not_taken(label2)
 ;; block2:
-;;   ld t3,0(a1)
-;;   add t3,t3,a6
-;;   lw a0,0(t3)
+;;   ld t4,0(a1)
+;;   add t4,t4,t3
+;;   lw a0,0(t4)
 ;;   j label3
 ;; block3:
 ;;   ret

cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i32_access_0x1000_offset.wat

@@ -41,19 +41,20 @@
 
 ;; function u0:0:
 ;; block0:
-;;   uext.w t0,a0
+;;   slli t0,a0,32
+;;   srli t2,t0,32
 ;;   ld t1,8(a2)
-;;   lui t4,1048575
-;;   addi t4,t4,4092
-;;   add t2,t1,t4
-;;   ugt t1,t0,t2##ty=i64
+;;   lui t0,1048575
+;;   addi t0,t0,4092
+;;   add a0,t1,t0
+;;   ugt t1,t2,a0##ty=i64
 ;;   bne t1,zero,taken(label1),not_taken(label2)
 ;; block2:
-;;   ld t2,0(a2)
-;;   add t2,t2,t0
-;;   lui t1,1
-;;   add a0,t2,t1
-;;   sw a1,0(a0)
+;;   ld a0,0(a2)
+;;   add a0,a0,t2
+;;   lui t2,1
+;;   add a2,a0,t2
+;;   sw a1,0(a2)
 ;;   j label3
 ;; block3:
 ;;   ret
@@ -62,19 +63,20 @@
 ;;
 ;; function u0:1:
 ;; block0:
-;;   uext.w t0,a0
+;;   slli t0,a0,32
+;;   srli t2,t0,32
 ;;   ld t1,8(a1)
-;;   lui t4,1048575
-;;   addi t4,t4,4092
-;;   add t2,t1,t4
-;;   ugt t1,t0,t2##ty=i64
+;;   lui t0,1048575
+;;   addi t0,t0,4092
+;;   add a0,t1,t0
+;;   ugt t1,t2,a0##ty=i64
 ;;   bne t1,zero,taken(label1),not_taken(label2)
 ;; block2:
-;;   ld t2,0(a1)
-;;   add t2,t2,t0
-;;   lui t1,1
-;;   add a0,t2,t1
-;;   lw a0,0(a0)
+;;   ld a0,0(a1)
+;;   add a0,a0,t2
+;;   lui t2,1
+;;   add a1,a0,t2
+;;   lw a0,0(a1)
 ;;   j label3
 ;; block3:
 ;;   ret

cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i32_access_0xffff0000_offset.wat

@@ -41,19 +41,20 @@
 
 ;; function u0:0:
 ;; block0:
-;;   uext.w t0,a0
-;;   auipc t3,0; ld t3,12(t3); j 12; .8byte 0xffff0004
-;;   add t1,t0,t3
-;;   ult t2,t1,t0##ty=i64
-;;   trap_if t2,heap_oob
-;;   ld t2,8(a2)
-;;   ugt t1,t1,t2##ty=i64
-;;   bne t1,zero,taken(label1),not_taken(label2)
+;;   slli t0,a0,32
+;;   srli t2,t0,32
+;;   auipc t4,0; ld t4,12(t4); j 12; .8byte 0xffff0004
+;;   add t1,t2,t4
+;;   ult a0,t1,t2##ty=i64
+;;   trap_if a0,heap_oob
+;;   ld a0,8(a2)
+;;   ugt a0,t1,a0##ty=i64
+;;   bne a0,zero,taken(label1),not_taken(label2)
 ;; block2:
-;;   ld a0,0(a2)
-;;   add a0,a0,t0
-;;   auipc t2,0; ld t2,12(t2); j 12; .8byte 0xffff0000
-;;   add a2,a0,t2
+;;   ld a2,0(a2)
+;;   add a2,a2,t2
+;;   auipc a0,0; ld a0,12(a0); j 12; .8byte 0xffff0000
+;;   add a2,a2,a0
 ;;   sw a1,0(a2)
 ;;   j label3
 ;; block3:
@@ -63,20 +64,21 @@
 ;;
 ;; function u0:1:
 ;; block0:
-;;   uext.w t0,a0
-;;   auipc t3,0; ld t3,12(t3); j 12; .8byte 0xffff0004
-;;   add t1,t0,t3
-;;   ult t2,t1,t0##ty=i64
-;;   trap_if t2,heap_oob
-;;   ld t2,8(a1)
-;;   ugt t1,t1,t2##ty=i64
-;;   bne t1,zero,taken(label1),not_taken(label2)
+;;   slli t0,a0,32
+;;   srli t2,t0,32
+;;   auipc t4,0; ld t4,12(t4); j 12; .8byte 0xffff0004
+;;   add t1,t2,t4
+;;   ult a0,t1,t2##ty=i64
+;;   trap_if a0,heap_oob
+;;   ld a0,8(a1)
+;;   ugt a0,t1,a0##ty=i64
+;;   bne a0,zero,taken(label1),not_taken(label2)
 ;; block2:
-;;   ld a0,0(a1)
-;;   add a0,a0,t0
-;;   auipc t2,0; ld t2,12(t2); j 12; .8byte 0xffff0000
-;;   add a1,a0,t2
-;;   lw a0,0(a1)
+;;   ld a1,0(a1)
+;;   add a1,a1,t2
+;;   auipc a0,0; ld a0,12(a0); j 12; .8byte 0xffff0000
+;;   add a2,a1,a0
+;;   lw a0,0(a2)
 ;;   j label3
 ;; block3:
 ;;   ret

cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0_offset.wat

@@ -41,14 +41,15 @@
 
 ;; function u0:0:
 ;; block0:
-;;   uext.w a5,a0
+;;   slli a5,a0,32
+;;   srli a7,a5,32
 ;;   ld a6,8(a2)
-;;   uge a6,a5,a6##ty=i64
+;;   uge a6,a7,a6##ty=i64
 ;;   bne a6,zero,taken(label1),not_taken(label2)
 ;; block2:
-;;   ld a7,0(a2)
-;;   add a7,a7,a5
-;;   sb a1,0(a7)
+;;   ld t3,0(a2)
+;;   add t3,t3,a7
+;;   sb a1,0(t3)
 ;;   j label3
 ;; block3:
 ;;   ret
@@ -57,14 +58,15 @@
 ;;
 ;; function u0:1:
 ;; block0:
-;;   uext.w a5,a0
+;;   slli a5,a0,32
+;;   srli a7,a5,32
 ;;   ld a6,8(a1)
-;;   uge a6,a5,a6##ty=i64
+;;   uge a6,a7,a6##ty=i64
 ;;   bne a6,zero,taken(label1),not_taken(label2)
 ;; block2:
-;;   ld a7,0(a1)
-;;   add a7,a7,a5
-;;   lbu a0,0(a7)
+;;   ld t3,0(a1)
+;;   add t3,t3,a7
+;;   lbu a0,0(t3)
 ;;   j label3
 ;; block3:
 ;;   ret

cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0x1000_offset.wat

@@ -41,19 +41,20 @@
 
 ;; function u0:0:
 ;; block0:
-;;   uext.w t0,a0
+;;   slli t0,a0,32
+;;   srli t2,t0,32
 ;;   ld t1,8(a2)
-;;   lui t4,1048575
-;;   addi t4,t4,4095
-;;   add t2,t1,t4
-;;   ugt t1,t0,t2##ty=i64
+;;   lui t0,1048575
+;;   addi t0,t0,4095
+;;   add a0,t1,t0
+;;   ugt t1,t2,a0##ty=i64
 ;;   bne t1,zero,taken(label1),not_taken(label2)
 ;; block2:
-;;   ld t2,0(a2)
-;;   add t2,t2,t0
-;;   lui t1,1
-;;   add a0,t2,t1
-;;   sb a1,0(a0)
+;;   ld a0,0(a2)
+;;   add a0,a0,t2
+;;   lui t2,1
+;;   add a2,a0,t2
+;;   sb a1,0(a2)
 ;;   j label3
 ;; block3:
 ;;   ret
@@ -62,19 +63,20 @@
 ;;
 ;; function u0:1:
 ;; block0:
-;;   uext.w t0,a0
+;;   slli t0,a0,32
+;;   srli t2,t0,32
 ;;   ld t1,8(a1)
-;;   lui t4,1048575
-;;   addi t4,t4,4095
-;;   add t2,t1,t4
-;;   ugt t1,t0,t2##ty=i64
+;;   lui t0,1048575
+;;   addi t0,t0,4095
+;;   add a0,t1,t0
+;;   ugt t1,t2,a0##ty=i64
 ;;   bne t1,zero,taken(label1),not_taken(label2)
 ;; block2:
-;;   ld t2,0(a1)
-;;   add t2,t2,t0
-;;   lui t1,1
-;;   add a0,t2,t1
-;;   lbu a0,0(a0)
+;;   ld a0,0(a1)
+;;   add a0,a0,t2
+;;   lui t2,1
+;;   add a1,a0,t2
+;;   lbu a0,0(a1)
 ;;   j label3
 ;; block3:
 ;;   ret

cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat

@@ -41,19 +41,20 @@
 
 ;; function u0:0:
 ;; block0:
-;;   uext.w t0,a0
-;;   auipc t3,0; ld t3,12(t3); j 12; .8byte 0xffff0001
-;;   add t1,t0,t3
-;;   ult t2,t1,t0##ty=i64
-;;   trap_if t2,heap_oob
-;;   ld t2,8(a2)
-;;   ugt t1,t1,t2##ty=i64
-;;   bne t1,zero,taken(label1),not_taken(label2)
+;;   slli t0,a0,32
+;;   srli t2,t0,32
+;;   auipc t4,0; ld t4,12(t4); j 12; .8byte 0xffff0001
+;;   add t1,t2,t4
+;;   ult a0,t1,t2##ty=i64
+;;   trap_if a0,heap_oob
+;;   ld a0,8(a2)
+;;   ugt a0,t1,a0##ty=i64
+;;   bne a0,zero,taken(label1),not_taken(label2)
 ;; block2:
-;;   ld a0,0(a2)
-;;   add a0,a0,t0
-;;   auipc t2,0; ld t2,12(t2); j 12; .8byte 0xffff0000
-;;   add a2,a0,t2
+;;   ld a2,0(a2)
+;;   add a2,a2,t2
+;;   auipc a0,0; ld a0,12(a0); j 12; .8byte 0xffff0000
+;;   add a2,a2,a0
 ;;   sb a1,0(a2)
 ;;   j label3
 ;; block3:
@@ -63,20 +64,21 @@
 ;;
 ;; function u0:1:
 ;; block0:
-;;   uext.w t0,a0
-;;   auipc t3,0; ld t3,12(t3); j 12; .8byte 0xffff0001
-;;   add t1,t0,t3
-;;   ult t2,t1,t0##ty=i64
-;;   trap_if t2,heap_oob
-;;   ld t2,8(a1)
-;;   ugt t1,t1,t2##ty=i64
-;;   bne t1,zero,taken(label1),not_taken(label2)
+;;   slli t0,a0,32
+;;   srli t2,t0,32
+;;   auipc t4,0; ld t4,12(t4); j 12; .8byte 0xffff0001
+;;   add t1,t2,t4
+;;   ult a0,t1,t2##ty=i64
+;;   trap_if a0,heap_oob
+;;   ld a0,8(a1)
+;;   ugt a0,t1,a0##ty=i64
+;;   bne a0,zero,taken(label1),not_taken(label2)
 ;; block2:
-;;   ld a0,0(a1)
-;;   add a0,a0,t0
-;;   auipc t2,0; ld t2,12(t2); j 12; .8byte 0xffff0000
-;;   add a1,a0,t2
-;;   lbu a0,0(a1)
+;;   ld a1,0(a1)
+;;   add a1,a1,t2
+;;   auipc a0,0; ld a0,12(a0); j 12; .8byte 0xffff0000
+;;   add a2,a1,a0
+;;   lbu a0,0(a2)
 ;;   j label3
 ;; block3:
 ;;   ret

cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i32_access_0_offset.wat

@@ -41,30 +41,32 @@
 
 ;; function u0:0:
 ;; block0:
-;;   uext.w t3,a0
+;;   slli t3,a0,32
+;;   srli t0,t3,32
 ;;   ld t4,8(a2)
 ;;   addi t4,t4,-4
-;;   ld t0,0(a2)
-;;   add t0,t0,t3
-;;   ugt a7,t3,t4##ty=i64
-;;   li t4,0
-;;   selectif_spectre_guard t3,t4,t0##test=a7
-;;   sw a1,0(t3)
+;;   ld t1,0(a2)
+;;   add t1,t1,t0
+;;   ugt t3,t0,t4##ty=i64
+;;   li t0,0
+;;   selectif_spectre_guard t4,t0,t1##test=t3
+;;   sw a1,0(t4)
 ;;   j label1
 ;; block1:
 ;;   ret
 ;;
 ;; function u0:1:
 ;; block0:
-;;   uext.w t3,a0
+;;   slli t3,a0,32
+;;   srli t0,t3,32
 ;;   ld t4,8(a1)
 ;;   addi t4,t4,-4
-;;   ld t0,0(a1)
-;;   add t0,t0,t3
-;;   ugt a7,t3,t4##ty=i64
-;;   li t4,0
-;;   selectif_spectre_guard t3,t4,t0##test=a7
-;;   lw a0,0(t3)
+;;   ld t1,0(a1)
+;;   add t1,t1,t0
+;;   ugt t3,t0,t4##ty=i64
+;;   li t0,0
+;;   selectif_spectre_guard t4,t0,t1##test=t3
+;;   lw a0,0(t4)
 ;;   j label1
 ;; block1:
 ;;   ret

cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i32_access_0x1000_offset.wat

@@ -41,38 +41,40 @@
 
 ;; function u0:0:
 ;; block0:
-;;   uext.w t2,a0
+;;   slli t2,a0,32
+;;   srli a3,t2,32
 ;;   ld a0,8(a2)
-;;   lui t1,1048575
-;;   addi t1,t1,4092
-;;   add a3,a0,t1
+;;   lui t2,1048575
+;;   addi t2,t2,4092
+;;   add a4,a0,t2
 ;;   ld a0,0(a2)
-;;   add a0,a0,t2
-;;   lui t1,1
-;;   add a0,a0,t1
-;;   ugt t1,t2,a3##ty=i64
-;;   li a2,0
-;;   selectif_spectre_guard t2,a2,a0##test=t1
-;;   sw a1,0(t2)
+;;   add a0,a0,a3
+;;   lui t2,1
+;;   add a2,a0,t2
+;;   ugt t2,a3,a4##ty=i64
+;;   li a3,0
+;;   selectif_spectre_guard a0,a3,a2##test=t2
+;;   sw a1,0(a0)
 ;;   j label1
 ;; block1:
 ;;   ret
 ;;
 ;; function u0:1:
 ;; block0:
-;;   uext.w t2,a0
+;;   slli t2,a0,32
+;;   srli a2,t2,32
 ;;   ld a0,8(a1)
-;;   lui t1,1048575
-;;   addi t1,t1,4092
-;;   add a2,a0,t1
+;;   lui t2,1048575
+;;   addi t2,t2,4092
+;;   add a3,a0,t2
 ;;   ld a0,0(a1)
-;;   add a0,a0,t2
-;;   lui t1,1
-;;   add a0,a0,t1
-;;   ugt t1,t2,a2##ty=i64
-;;   li a1,0
-;;   selectif_spectre_guard t2,a1,a0##test=t1
-;;   lw a0,0(t2)
+;;   add a0,a0,a2
+;;   lui t2,1
+;;   add a1,a0,t2
+;;   ugt t2,a2,a3##ty=i64
+;;   li a2,0
+;;   selectif_spectre_guard a0,a2,a1##test=t2
+;;   lw a0,0(a0)
 ;;   j label1
 ;; block1:
 ;;   ret

cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i32_access_0xffff0000_offset.wat

@@ -41,40 +41,42 @@
 
 ;; function u0:0:
 ;; block0:
-;;   uext.w a0,a0
-;;   auipc t0,0; ld t0,12(t0); j 12; .8byte 0xffff0004
-;;   add t2,a0,t0
-;;   ult a3,t2,a0##ty=i64
-;;   trap_if a3,heap_oob
-;;   ld a3,8(a2)
+;;   slli t2,a0,32
+;;   srli a3,t2,32
+;;   auipc t1,0; ld t1,12(t1); j 12; .8byte 0xffff0004
+;;   add a0,a3,t1
+;;   ult a4,a0,a3##ty=i64
+;;   trap_if a4,heap_oob
+;;   ld a4,8(a2)
 ;;   ld a2,0(a2)
-;;   add a0,a2,a0
-;;   auipc a2,0; ld a2,12(a2); j 12; .8byte 0xffff0000
-;;   add a2,a0,a2
-;;   ugt t2,t2,a3##ty=i64
+;;   add a2,a2,a3
+;;   auipc a3,0; ld a3,12(a3); j 12; .8byte 0xffff0000
+;;   add a2,a2,a3
+;;   ugt a0,a0,a4##ty=i64
 ;;   li a3,0
-;;   selectif_spectre_guard a0,a3,a2##test=t2
-;;   sw a1,0(a0)
+;;   selectif_spectre_guard a4,a3,a2##test=a0
+;;   sw a1,0(a4)
 ;;   j label1
 ;; block1:
 ;;   ret
 ;;
 ;; function u0:1:
 ;; block0:
-;;   uext.w a0,a0
-;;   auipc t0,0; ld t0,12(t0); j 12; .8byte 0xffff0004
-;;   add t2,a0,t0
-;;   ult a2,t2,a0##ty=i64
-;;   trap_if a2,heap_oob
-;;   ld a2,8(a1)
+;;   slli t2,a0,32
+;;   srli a2,t2,32
+;;   auipc t1,0; ld t1,12(t1); j 12; .8byte 0xffff0004
+;;   add a0,a2,t1
+;;   ult a3,a0,a2##ty=i64
+;;   trap_if a3,heap_oob
+;;   ld a3,8(a1)
 ;;   ld a1,0(a1)
-;;   add a0,a1,a0
-;;   auipc a1,0; ld a1,12(a1); j 12; .8byte 0xffff0000
-;;   add a1,a0,a1
-;;   ugt t2,t2,a2##ty=i64
-;;   li a2,0
-;;   selectif_spectre_guard a0,a2,a1##test=t2
-;;   lw a0,0(a0)
+;;   add a1,a1,a2
+;;   auipc a2,0; ld a2,12(a2); j 12; .8byte 0xffff0000
+;;   add a2,a1,a2
+;;   ugt a0,a0,a3##ty=i64
+;;   li a3,0
+;;   selectif_spectre_guard a1,a3,a2##test=a0
+;;   lw a0,0(a1)
 ;;   j label1
 ;; block1:
 ;;   ret

cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat

@@ -41,28 +41,30 @@
 
 ;; function u0:0:
 ;; block0:
-;;   uext.w a7,a0
+;;   slli a7,a0,32
+;;   srli t4,a7,32
 ;;   ld t3,8(a2)
-;;   ld t4,0(a2)
-;;   add t4,t4,a7
-;;   uge a6,a7,t3##ty=i64
-;;   li t3,0
-;;   selectif_spectre_guard a7,t3,t4##test=a6
-;;   sb a1,0(a7)
+;;   ld t0,0(a2)
+;;   add t0,t0,t4
+;;   uge a7,t4,t3##ty=i64
+;;   li t4,0
+;;   selectif_spectre_guard t3,t4,t0##test=a7
+;;   sb a1,0(t3)
 ;;   j label1
 ;; block1:
 ;;   ret
 ;;
 ;; function u0:1:
 ;; block0:
-;;   uext.w a7,a0
+;;   slli a7,a0,32
+;;   srli t4,a7,32
 ;;   ld t3,8(a1)
-;;   ld t4,0(a1)
-;;   add t4,t4,a7
-;;   uge a6,a7,t3##ty=i64
-;;   li t3,0
-;;   selectif_spectre_guard a7,t3,t4##test=a6
-;;   lbu a0,0(a7)
+;;   ld t0,0(a1)
+;;   add t0,t0,t4
+;;   uge a7,t4,t3##ty=i64
+;;   li t4,0
+;;   selectif_spectre_guard t3,t4,t0##test=a7
+;;   lbu a0,0(t3)
 ;;   j label1
 ;; block1:
 ;;   ret

cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat

@@ -41,38 +41,40 @@
 
 ;; function u0:0:
 ;; block0:
-;;   uext.w t2,a0
+;;   slli t2,a0,32
+;;   srli a3,t2,32
 ;;   ld a0,8(a2)
-;;   lui t1,1048575
-;;   addi t1,t1,4095
-;;   add a3,a0,t1
+;;   lui t2,1048575
+;;   addi t2,t2,4095
+;;   add a4,a0,t2
 ;;   ld a0,0(a2)
-;;   add a0,a0,t2
-;;   lui t1,1
-;;   add a0,a0,t1
-;;   ugt t1,t2,a3##ty=i64
-;;   li a2,0
-;;   selectif_spectre_guard t2,a2,a0##test=t1
-;;   sb a1,0(t2)
+;;   add a0,a0,a3
+;;   lui t2,1
+;;   add a2,a0,t2
+;;   ugt t2,a3,a4##ty=i64
+;;   li a3,0
+;;   selectif_spectre_guard a0,a3,a2##test=t2
+;;   sb a1,0(a0)
 ;;   j label1
 ;; block1:
 ;;   ret
 ;;
 ;; function u0:1:
 ;; block0:
-;;   uext.w t2,a0
+;;   slli t2,a0,32
+;;   srli a2,t2,32
 ;;   ld a0,8(a1)
-;;   lui t1,1048575
-;;   addi t1,t1,4095
-;;   add a2,a0,t1
+;;   lui t2,1048575
+;;   addi t2,t2,4095
+;;   add a3,a0,t2
 ;;   ld a0,0(a1)
-;;   add a0,a0,t2
-;;   lui t1,1
-;;   add a0,a0,t1
-;;   ugt t1,t2,a2##ty=i64
-;;   li a1,0
-;;   selectif_spectre_guard t2,a1,a0##test=t1
-;;   lbu a0,0(t2)
+;;   add a0,a0,a2
+;;   lui t2,1
+;;   add a1,a0,t2
+;;   ugt t2,a2,a3##ty=i64
+;;   li a2,0
+;;   selectif_spectre_guard a0,a2,a1##test=t2
+;;   lbu a0,0(a0)
 ;;   j label1
 ;; block1:
 ;;   ret

cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat

@@ -41,40 +41,42 @@
 
 ;; function u0:0:
 ;; block0:
-;;   uext.w a0,a0
-;;   auipc t0,0; ld t0,12(t0); j 12; .8byte 0xffff0001
-;;   add t2,a0,t0
-;;   ult a3,t2,a0##ty=i64
-;;   trap_if a3,heap_oob
-;;   ld a3,8(a2)
+;;   slli t2,a0,32
+;;   srli a3,t2,32
+;;   auipc t1,0; ld t1,12(t1); j 12; .8byte 0xffff0001
+;;   add a0,a3,t1
+;;   ult a4,a0,a3##ty=i64
+;;   trap_if a4,heap_oob
+;;   ld a4,8(a2)
 ;;   ld a2,0(a2)
-;;   add a0,a2,a0
-;;   auipc a2,0; ld a2,12(a2); j 12; .8byte 0xffff0000
-;;   add a2,a0,a2
-;;   ugt t2,t2,a3##ty=i64
+;;   add a2,a2,a3
+;;   auipc a3,0; ld a3,12(a3); j 12; .8byte 0xffff0000
+;;   add a2,a2,a3
+;;   ugt a0,a0,a4##ty=i64
 ;;   li a3,0
-;;   selectif_spectre_guard a0,a3,a2##test=t2
-;;   sb a1,0(a0)
+;;   selectif_spectre_guard a4,a3,a2##test=a0
+;;   sb a1,0(a4)
 ;;   j label1
 ;; block1:
 ;;   ret
 ;;
 ;; function u0:1:
 ;; block0:
-;;   uext.w a0,a0
-;;   auipc t0,0; ld t0,12(t0); j 12; .8byte 0xffff0001
-;;   add t2,a0,t0
-;;   ult a2,t2,a0##ty=i64
-;;   trap_if a2,heap_oob
-;;   ld a2,8(a1)
+;;   slli t2,a0,32
+;;   srli a2,t2,32
+;;   auipc t1,0; ld t1,12(t1); j 12; .8byte 0xffff0001
+;;   add a0,a2,t1
+;;   ult a3,a0,a2##ty=i64
+;;   trap_if a3,heap_oob
+;;   ld a3,8(a1)
 ;;   ld a1,0(a1)
-;;   add a0,a1,a0
-;;   auipc a1,0; ld a1,12(a1); j 12; .8byte 0xffff0000
-;;   add a1,a0,a1
-;;   ugt t2,t2,a2##ty=i64
-;;   li a2,0
-;;   selectif_spectre_guard a0,a2,a1##test=t2
-;;   lbu a0,0(a0)
+;;   add a1,a1,a2
+;;   auipc a2,0; ld a2,12(a2); j 12; .8byte 0xffff0000
+;;   add a2,a1,a2
+;;   ugt a0,a0,a3##ty=i64
+;;   li a3,0
+;;   selectif_spectre_guard a1,a3,a2##test=a0
+;;   lbu a0,0(a1)
 ;;   j label1
 ;; block1:
 ;;   ret

cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0_guard_no_spectre_i32_access_0_offset.wat

@@ -39,15 +39,16 @@
 
 ;; function u0:0:
 ;; block0:
-;;   uext.w a6,a0
-;;   lui a5,65536
-;;   addi a5,a5,4092
-;;   ugt t3,a6,a5##ty=i64
-;;   bne t3,zero,taken(label1),not_taken(label2)
+;;   slli a6,a0,32
+;;   srli t3,a6,32
+;;   lui a6,65536
+;;   addi a6,a6,4092
+;;   ugt t4,t3,a6##ty=i64
+;;   bne t4,zero,taken(label1),not_taken(label2)
 ;; block2:
-;;   ld t3,0(a2)
-;;   add t3,t3,a6
-;;   sw a1,0(t3)
+;;   ld t4,0(a2)
+;;   add t4,t4,t3
+;;   sw a1,0(t4)
 ;;   j label3
 ;; block3:
 ;;   ret
@@ -56,15 +57,16 @@
 ;;
 ;; function u0:1:
 ;; block0:
-;;   uext.w a6,a0
-;;   lui a5,65536
-;;   addi a5,a5,4092
-;;   ugt t3,a6,a5##ty=i64
-;;   bne t3,zero,taken(label1),not_taken(label2)
+;;   slli a6,a0,32
+;;   srli t3,a6,32
+;;   lui a6,65536
+;;   addi a6,a6,4092
+;;   ugt t4,t3,a6##ty=i64
+;;   bne t4,zero,taken(label1),not_taken(label2)
 ;; block2:
-;;   ld t3,0(a1)
-;;   add t3,t3,a6
-;;   lw a0,0(t3)
+;;   ld t4,0(a1)
+;;   add t4,t4,t3
+;;   lw a0,0(t4)
 ;;   j label3
 ;; block3:
 ;;   ret

cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0_guard_no_spectre_i32_access_0x1000_offset.wat

@@ -39,17 +39,18 @@
 
 ;; function u0:0:
 ;; block0:
-;;   uext.w t3,a0
-;;   lui a7,65535
-;;   addi a7,a7,4092
-;;   ugt t0,t3,a7##ty=i64
-;;   bne t0,zero,taken(label1),not_taken(label2)
+;;   slli t3,a0,32
+;;   srli t0,t3,32
+;;   lui t3,65535
+;;   addi t3,t3,4092
+;;   ugt t1,t0,t3##ty=i64
+;;   bne t1,zero,taken(label1),not_taken(label2)
 ;; block2:
-;;   ld t0,0(a2)
-;;   add t0,t0,t3
-;;   lui t4,1
-;;   add t1,t0,t4
-;;   sw a1,0(t1)
+;;   ld t1,0(a2)
+;;   add t1,t1,t0
+;;   lui t0,1
+;;   add t2,t1,t0
+;;   sw a1,0(t2)
 ;;   j label3
 ;; block3:
 ;;   ret
@@ -58,17 +59,18 @@
 ;;
 ;; function u0:1:
 ;; block0:
-;;   uext.w t3,a0
-;;   lui a7,65535
-;;   addi a7,a7,4092
-;;   ugt t0,t3,a7##ty=i64
-;;   bne t0,zero,taken(label1),not_taken(label2)
+;;   slli t3,a0,32
+;;   srli t0,t3,32
+;;   lui t3,65535
+;;   addi t3,t3,4092
+;;   ugt t1,t0,t3##ty=i64
+;;   bne t1,zero,taken(label1),not_taken(label2)
 ;; block2:
-;;   ld t0,0(a1)
-;;   add t0,t0,t3
-;;   lui t4,1
-;;   add t1,t0,t4
-;;   lw a0,0(t1)
+;;   ld t1,0(a1)
+;;   add t1,t1,t0
+;;   lui t0,1
+;;   add t2,t1,t0
+;;   lw a0,0(t2)
 ;;   j label3
 ;; block3:
 ;;   ret

cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0_guard_no_spectre_i8_access_0_offset.wat

@@ -39,15 +39,16 @@
 
 ;; function u0:0:
 ;; block0:
-;;   uext.w a6,a0
-;;   lui a5,65536
-;;   addi a5,a5,4095
-;;   ugt t3,a6,a5##ty=i64
-;;   bne t3,zero,taken(label1),not_taken(label2)
+;;   slli a6,a0,32
+;;   srli t3,a6,32
+;;   lui a6,65536
+;;   addi a6,a6,4095
+;;   ugt t4,t3,a6##ty=i64
+;;   bne t4,zero,taken(label1),not_taken(label2)
 ;; block2:
-;;   ld t3,0(a2)
-;;   add t3,t3,a6
-;;   sb a1,0(t3)
+;;   ld t4,0(a2)
+;;   add t4,t4,t3
+;;   sb a1,0(t4)
 ;;   j label3
 ;; block3:
 ;;   ret
@@ -56,15 +57,16 @@
 ;;
 ;; function u0:1:
 ;; block0:
-;;   uext.w a6,a0
-;;   lui a5,65536
-;;   addi a5,a5,4095
-;;   ugt t3,a6,a5##ty=i64
-;;   bne t3,zero,taken(label1),not_taken(label2)
+;;   slli a6,a0,32
+;;   srli t3,a6,32
+;;   lui a6,65536
+;;   addi a6,a6,4095
+;;   ugt t4,t3,a6##ty=i64
+;;   bne t4,zero,taken(label1),not_taken(label2)
 ;; block2:
-;;   ld t3,0(a1)
-;;   add t3,t3,a6
-;;   lbu a0,0(t3)
+;;   ld t4,0(a1)
+;;   add t4,t4,t3
+;;   lbu a0,0(t4)
 ;;   j label3
 ;; block3:
 ;;   ret

cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0_guard_no_spectre_i8_access_0x1000_offset.wat

@@ -39,17 +39,18 @@
 
 ;; function u0:0:
 ;; block0:
-;;   uext.w t3,a0
-;;   lui a7,65535
-;;   addi a7,a7,4095
-;;   ugt t0,t3,a7##ty=i64
-;;   bne t0,zero,taken(label1),not_taken(label2)
+;;   slli t3,a0,32
+;;   srli t0,t3,32
+;;   lui t3,65535
+;;   addi t3,t3,4095
+;;   ugt t1,t0,t3##ty=i64
+;;   bne t1,zero,taken(label1),not_taken(label2)
 ;; block2:
-;;   ld t0,0(a2)
-;;   add t0,t0,t3
-;;   lui t4,1
-;;   add t1,t0,t4
-;;   sb a1,0(t1)
+;;   ld t1,0(a2)
+;;   add t1,t1,t0
+;;   lui t0,1
+;;   add t2,t1,t0
+;;   sb a1,0(t2)
 ;;   j label3
 ;; block3:
 ;;   ret
@@ -58,17 +59,18 @@
 ;;
 ;; function u0:1:
 ;; block0:
-;;   uext.w t3,a0
-;;   lui a7,65535
-;;   addi a7,a7,4095
-;;   ugt t0,t3,a7##ty=i64
-;;   bne t0,zero,taken(label1),not_taken(label2)
+;;   slli t3,a0,32
+;;   srli t0,t3,32
+;;   lui t3,65535
+;;   addi t3,t3,4095
+;;   ugt t1,t0,t3##ty=i64
+;;   bne t1,zero,taken(label1),not_taken(label2)
 ;; block2:
-;;   ld t0,0(a1)
-;;   add t0,t0,t3
-;;   lui t4,1
-;;   add t1,t0,t4
-;;   lbu a0,0(t1)
+;;   ld t1,0(a1)
+;;   add t1,t1,t0
+;;   lui t0,1
+;;   add t2,t1,t0
+;;   lbu a0,0(t2)
 ;;   j label3
 ;; block3:
 ;;   ret

cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0_guard_yes_spectre_i32_access_0_offset.wat

@@ -39,30 +39,32 @@
 
 ;; function u0:0:
 ;; block0:
-;;   uext.w t3,a0
+;;   slli t3,a0,32
+;;   srli t0,t3,32
 ;;   ld t4,0(a2)
-;;   add t4,t4,t3
-;;   lui a6,65536
-;;   addi a6,a6,4092
-;;   ugt t0,t3,a6##ty=i64
-;;   li t1,0
-;;   selectif_spectre_guard t3,t1,t4##test=t0
-;;   sw a1,0(t3)
+;;   add t4,t4,t0
+;;   lui a7,65536
+;;   addi a7,a7,4092
+;;   ugt t0,t0,a7##ty=i64
+;;   li t2,0
+;;   selectif_spectre_guard t1,t2,t4##test=t0
+;;   sw a1,0(t1)
 ;;   j label1
 ;; block1:
 ;;   ret
 ;;
 ;; function u0:1:
 ;; block0:
-;;   uext.w t3,a0
+;;   slli t3,a0,32
+;;   srli t0,t3,32
 ;;   ld t4,0(a1)
-;;   add t4,t4,t3
-;;   lui a6,65536
-;;   addi a6,a6,4092
-;;   ugt t0,t3,a6##ty=i64
-;;   li t1,0
-;;   selectif_spectre_guard t3,t1,t4##test=t0
-;;   lw a0,0(t3)
+;;   add t4,t4,t0
+;;   lui a7,65536
+;;   addi a7,a7,4092
+;;   ugt t0,t0,a7##ty=i64
+;;   li t2,0
+;;   selectif_spectre_guard t1,t2,t4##test=t0
+;;   lw a0,0(t1)
 ;;   j label1
 ;; block1:
 ;;   ret

cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0_guard_yes_spectre_i32_access_0x1000_offset.wat

@@ -39,34 +39,36 @@
 
 ;; function u0:0:
 ;; block0:
-;;   uext.w t0,a0
+;;   slli t0,a0,32
+;;   srli t2,t0,32
 ;;   ld t1,0(a2)
-;;   add t1,t1,t0
-;;   lui t4,1
-;;   add t1,t1,t4
-;;   lui t3,65535
-;;   addi t3,t3,4092
-;;   ugt t2,t0,t3##ty=i64
-;;   li a0,0
-;;   selectif_spectre_guard t0,a0,t1##test=t2
-;;   sw a1,0(t0)
+;;   add t1,t1,t2
+;;   lui t0,1
+;;   add a0,t1,t0
+;;   lui t4,65535
+;;   addi t4,t4,4092
+;;   ugt t2,t2,t4##ty=i64
+;;   li a2,0
+;;   selectif_spectre_guard t1,a2,a0##test=t2
+;;   sw a1,0(t1)
 ;;   j label1
 ;; block1:
 ;;   ret
 ;;
 ;; function u0:1:
 ;; block0:
-;;   uext.w t0,a0
+;;   slli t0,a0,32
+;;   srli t2,t0,32
 ;;   ld t1,0(a1)
-;;   add t1,t1,t0
-;;   lui t4,1
-;;   add t1,t1,t4
-;;   lui t3,65535
-;;   addi t3,t3,4092
-;;   ugt t2,t0,t3##ty=i64
-;;   li a0,0
-;;   selectif_spectre_guard t0,a0,t1##test=t2
-;;   lw a0,0(t0)
+;;   add t1,t1,t2
+;;   lui t0,1
+;;   add a0,t1,t0
+;;   lui t4,65535
+;;   addi t4,t4,4092
+;;   ugt t2,t2,t4##ty=i64
+;;   li a1,0
+;;   selectif_spectre_guard t1,a1,a0##test=t2
+;;   lw a0,0(t1)
 ;;   j label1
 ;; block1:
 ;;   ret

cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0_guard_yes_spectre_i8_access_0_offset.wat

@@ -39,30 +39,32 @@
 
 ;; function u0:0:
 ;; block0:
-;;   uext.w t3,a0
+;;   slli t3,a0,32
+;;   srli t0,t3,32
 ;;   ld t4,0(a2)
-;;   add t4,t4,t3
-;;   lui a6,65536
-;;   addi a6,a6,4095
-;;   ugt t0,t3,a6##ty=i64
-;;   li t1,0
-;;   selectif_spectre_guard t3,t1,t4##test=t0
-;;   sb a1,0(t3)
+;;   add t4,t4,t0
+;;   lui a7,65536
+;;   addi a7,a7,4095
+;;   ugt t0,t0,a7##ty=i64
+;;   li t2,0
+;;   selectif_spectre_guard t1,t2,t4##test=t0
+;;   sb a1,0(t1)
 ;;   j label1
 ;; block1:
 ;;   ret
 ;;
 ;; function u0:1:
 ;; block0:
-;;   uext.w t3,a0
+;;   slli t3,a0,32
+;;   srli t0,t3,32
 ;;   ld t4,0(a1)
-;;   add t4,t4,t3
-;;   lui a6,65536
-;;   addi a6,a6,4095
-;;   ugt t0,t3,a6##ty=i64
-;;   li t1,0
-;;   selectif_spectre_guard t3,t1,t4##test=t0
-;;   lbu a0,0(t3)
+;;   add t4,t4,t0
+;;   lui a7,65536
+;;   addi a7,a7,4095
+;;   ugt t0,t0,a7##ty=i64
+;;   li t2,0
+;;   selectif_spectre_guard t1,t2,t4##test=t0
+;;   lbu a0,0(t1)
 ;;   j label1
 ;; block1:
 ;;   ret

cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat

@@ -39,34 +39,36 @@
 
 ;; function u0:0:
 ;; block0:
-;;   uext.w t0,a0
+;;   slli t0,a0,32
+;;   srli t2,t0,32
 ;;   ld t1,0(a2)
-;;   add t1,t1,t0
-;;   lui t4,1
-;;   add t1,t1,t4
-;;   lui t3,65535
-;;   addi t3,t3,4095
-;;   ugt t2,t0,t3##ty=i64
-;;   li a0,0
-;;   selectif_spectre_guard t0,a0,t1##test=t2
-;;   sb a1,0(t0)
+;;   add t1,t1,t2
+;;   lui t0,1
+;;   add a0,t1,t0
+;;   lui t4,65535
+;;   addi t4,t4,4095
+;;   ugt t2,t2,t4##ty=i64
+;;   li a2,0
+;;   selectif_spectre_guard t1,a2,a0##test=t2
+;;   sb a1,0(t1)
 ;;   j label1
 ;; block1:
 ;;   ret
 ;;
 ;; function u0:1:
 ;; block0:
-;;   uext.w t0,a0
+;;   slli t0,a0,32
+;;   srli t2,t0,32
 ;;   ld t1,0(a1)
-;;   add t1,t1,t0
-;;   lui t4,1
-;;   add t1,t1,t4
-;;   lui t3,65535
-;;   addi t3,t3,4095
-;;   ugt t2,t0,t3##ty=i64
-;;   li a0,0
-;;   selectif_spectre_guard t0,a0,t1##test=t2
-;;   lbu a0,0(t0)
+;;   add t1,t1,t2
+;;   lui t0,1
+;;   add a0,t1,t0
+;;   lui t4,65535
+;;   addi t4,t4,4095
+;;   ugt t2,t2,t4##ty=i64
+;;   li a1,0
+;;   selectif_spectre_guard t1,a1,a0##test=t2
+;;   lbu a0,0(t1)
 ;;   j label1
 ;; block1:
 ;;   ret

cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0xffffffff_guard_no_spectre_i32_access_0_offset.wat

@@ -39,20 +39,22 @@
 
 ;; function u0:0:
 ;; block0:
-;;   uext.w a3,a0
+;;   slli a3,a0,32
+;;   srli a5,a3,32
 ;;   ld a4,0(a2)
-;;   add a3,a4,a3
-;;   sw a1,0(a3)
+;;   add a4,a4,a5
+;;   sw a1,0(a4)
 ;;   j label1
 ;; block1:
 ;;   ret
 ;;
 ;; function u0:1:
 ;; block0:
-;;   uext.w a3,a0
+;;   slli a3,a0,32
+;;   srli a5,a3,32
 ;;   ld a4,0(a1)
-;;   add a3,a4,a3
-;;   lw a0,0(a3)
+;;   add a4,a4,a5
+;;   lw a0,0(a4)
 ;;   j label1
 ;; block1:
 ;;   ret

cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0xffffffff_guard_no_spectre_i32_access_0x1000_offset.wat

@@ -39,24 +39,26 @@
 
 ;; function u0:0:
 ;; block0:
-;;   uext.w a5,a0
+;;   slli a5,a0,32
+;;   srli a7,a5,32
 ;;   ld a6,0(a2)
-;;   add a5,a6,a5
-;;   lui a4,1
-;;   add a6,a5,a4
-;;   sw a1,0(a6)
+;;   add a6,a6,a7
+;;   lui a5,1
+;;   add a7,a6,a5
+;;   sw a1,0(a7)
 ;;   j label1
 ;; block1:
 ;;   ret
 ;;
 ;; function u0:1:
 ;; block0:
-;;   uext.w a5,a0
+;;   slli a5,a0,32
+;;   srli a7,a5,32
 ;;   ld a6,0(a1)
-;;   add a5,a6,a5
-;;   lui a4,1
-;;   add a6,a5,a4
-;;   lw a0,0(a6)
+;;   add a6,a6,a7
+;;   lui a5,1
+;;   add a7,a6,a5
+;;   lw a0,0(a7)
 ;;   j label1
 ;; block1:
 ;;   ret

cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0_offset.wat

@@ -39,20 +39,22 @@
 
 ;; function u0:0:
 ;; block0:
-;;   uext.w a3,a0
+;;   slli a3,a0,32
+;;   srli a5,a3,32
 ;;   ld a4,0(a2)
-;;   add a3,a4,a3
-;;   sb a1,0(a3)
+;;   add a4,a4,a5
+;;   sb a1,0(a4)
 ;;   j label1
 ;; block1:
 ;;   ret
 ;;
 ;; function u0:1:
 ;; block0:
-;;   uext.w a3,a0
+;;   slli a3,a0,32
+;;   srli a5,a3,32
 ;;   ld a4,0(a1)
-;;   add a3,a4,a3
-;;   lbu a0,0(a3)
+;;   add a4,a4,a5
+;;   lbu a0,0(a4)
 ;;   j label1
 ;; block1:
 ;;   ret

cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0x1000_offset.wat

@@ -39,24 +39,26 @@
 
 ;; function u0:0:
 ;; block0:
-;;   uext.w a5,a0
+;;   slli a5,a0,32
+;;   srli a7,a5,32
 ;;   ld a6,0(a2)
-;;   add a5,a6,a5
-;;   lui a4,1
-;;   add a6,a5,a4
-;;   sb a1,0(a6)
+;;   add a6,a6,a7
+;;   lui a5,1
+;;   add a7,a6,a5
+;;   sb a1,0(a7)
 ;;   j label1
 ;; block1:
 ;;   ret
 ;;
 ;; function u0:1:
 ;; block0:
-;;   uext.w a5,a0
+;;   slli a5,a0,32
+;;   srli a7,a5,32
 ;;   ld a6,0(a1)
-;;   add a5,a6,a5
-;;   lui a4,1
-;;   add a6,a5,a4
-;;   lbu a0,0(a6)
+;;   add a6,a6,a7
+;;   lui a5,1
+;;   add a7,a6,a5
+;;   lbu a0,0(a7)
 ;;   j label1
 ;; block1:
 ;;   ret

cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0xffffffff_guard_yes_spectre_i32_access_0_offset.wat

@@ -39,20 +39,22 @@
 
 ;; function u0:0:
 ;; block0:
-;;   uext.w a3,a0
+;;   slli a3,a0,32
+;;   srli a5,a3,32
 ;;   ld a4,0(a2)
-;;   add a3,a4,a3
-;;   sw a1,0(a3)
+;;   add a4,a4,a5
+;;   sw a1,0(a4)
 ;;   j label1
 ;; block1:
 ;;   ret
 ;;
 ;; function u0:1:
 ;; block0:
-;;   uext.w a3,a0
+;;   slli a3,a0,32
+;;   srli a5,a3,32
 ;;   ld a4,0(a1)
-;;   add a3,a4,a3
-;;   lw a0,0(a3)
+;;   add a4,a4,a5
+;;   lw a0,0(a4)
 ;;   j label1
 ;; block1:
 ;;   ret

cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0xffffffff_guard_yes_spectre_i32_access_0x1000_offset.wat

@@ -39,24 +39,26 @@
 
 ;; function u0:0:
 ;; block0:
-;;   uext.w a5,a0
+;;   slli a5,a0,32
+;;   srli a7,a5,32
 ;;   ld a6,0(a2)
-;;   add a5,a6,a5
-;;   lui a4,1
-;;   add a6,a5,a4
-;;   sw a1,0(a6)
+;;   add a6,a6,a7
+;;   lui a5,1
+;;   add a7,a6,a5
+;;   sw a1,0(a7)
 ;;   j label1
 ;; block1:
 ;;   ret
 ;;
 ;; function u0:1:
 ;; block0:
-;;   uext.w a5,a0
+;;   slli a5,a0,32
+;;   srli a7,a5,32
 ;;   ld a6,0(a1)
-;;   add a5,a6,a5
-;;   lui a4,1
-;;   add a6,a5,a4
-;;   lw a0,0(a6)
+;;   add a6,a6,a7
+;;   lui a5,1
+;;   add a7,a6,a5
+;;   lw a0,0(a7)
 ;;   j label1
 ;; block1:
 ;;   ret

cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat

@@ -39,20 +39,22 @@
 
 ;; function u0:0:
 ;; block0:
-;;   uext.w a3,a0
+;;   slli a3,a0,32
+;;   srli a5,a3,32
 ;;   ld a4,0(a2)
-;;   add a3,a4,a3
-;;   sb a1,0(a3)
+;;   add a4,a4,a5
+;;   sb a1,0(a4)
 ;;   j label1
 ;; block1:
 ;;   ret
 ;;
 ;; function u0:1:
 ;; block0:
-;;   uext.w a3,a0
+;;   slli a3,a0,32
+;;   srli a5,a3,32
 ;;   ld a4,0(a1)
-;;   add a3,a4,a3
-;;   lbu a0,0(a3)
+;;   add a4,a4,a5
+;;   lbu a0,0(a4)
 ;;   j label1
 ;; block1:
 ;;   ret

cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat

@@ -39,24 +39,26 @@
 
 ;; function u0:0:
 ;; block0:
-;;   uext.w a5,a0
+;;   slli a5,a0,32
+;;   srli a7,a5,32
 ;;   ld a6,0(a2)
-;;   add a5,a6,a5
-;;   lui a4,1
-;;   add a6,a5,a4
-;;   sb a1,0(a6)
+;;   add a6,a6,a7
+;;   lui a5,1
+;;   add a7,a6,a5
+;;   sb a1,0(a7)
 ;;   j label1
 ;; block1:
 ;;   ret
 ;;
 ;; function u0:1:
 ;; block0:
-;;   uext.w a5,a0
+;;   slli a5,a0,32
+;;   srli a7,a5,32
 ;;   ld a6,0(a1)
-;;   add a5,a6,a5
-;;   lui a4,1
-;;   add a6,a5,a4
-;;   lbu a0,0(a6)
+;;   add a6,a6,a7
+;;   lui a5,1
+;;   add a7,a6,a5
+;;   lbu a0,0(a7)
 ;;   j label1
 ;; block1:
 ;;   ret

cranelift/filetests/filetests/runtests/extend.clif

@@ -4,6 +4,8 @@ target aarch64
 target s390x
 target x86_64
 target riscv64
+target riscv64 has_zbb
+target riscv64 has_zbkb
 
 ;;;; basic uextend
 

cranelift/filetests/filetests/runtests/i128-extend.clif

@@ -5,6 +5,8 @@ target aarch64
 target s390x
 target x86_64
 target riscv64
+target riscv64 has_zbb
+target riscv64 has_zbkb
 
 function %i128_uextend_i64(i64) -> i128 {
 block0(v0: i64):