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riscv64: Improve signed and zero extend codegen (#5844)

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* riscv64: Remove unused code

* riscv64: Group extend rules

* riscv64: Remove more unused rules

* riscv64: Cleanup existing extension rules

* riscv64: Move the existing Extend rules to ISLE

* riscv64: Use `sext.w` when extending

* riscv64: Remove duplicate extend tests

* riscv64: Use `zbb` instructions when extending values

* riscv64: Use `zbkb` extensions when zero extending

* riscv64: Enable additional tests for extend i128

* riscv64: Fix formatting for `Inst::Extend`

* riscv64: Reverse register for pack

* riscv64: Misc Cleanups

* riscv64: Cleanup extend rules
This commit is contained in:
Afonso Bordado
2023-02-22 17:41:14 +00:00
committed by GitHub
parent 6e6a1034d7
commit f6c6bc2155
68 changed files with 1922 additions and 1585 deletions
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4
cranelift/filetests/filetests/runtests/extend.clif
View File

@@ -3,7 +3,9 @@ test run
target aarch64
target s390x
target x86_64
target riscv64
target riscv64
target riscv64 has_zbb
target riscv64 has_zbkb
;;;; basic uextend

2
cranelift/filetests/filetests/runtests/i128-extend.clif
View File

@@ -5,6 +5,8 @@ target aarch64
target s390x
target x86_64
target riscv64
target riscv64 has_zbb
target riscv64 has_zbkb
function %i128_uextend_i64(i64) -> i128 {
block0(v0: i64):