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riscv64: Improve signed and zero extend codegen (#5844)

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* riscv64: Remove unused code

* riscv64: Group extend rules

* riscv64: Remove more unused rules

* riscv64: Cleanup existing extension rules

* riscv64: Move the existing Extend rules to ISLE

* riscv64: Use `sext.w` when extending

* riscv64: Remove duplicate extend tests

* riscv64: Use `zbb` instructions when extending values

* riscv64: Use `zbkb` extensions when zero extending

* riscv64: Enable additional tests for extend i128

* riscv64: Fix formatting for `Inst::Extend`

* riscv64: Reverse register for pack

* riscv64: Misc Cleanups

* riscv64: Cleanup extend rules
This commit is contained in:
Afonso Bordado
2023-02-22 17:41:14 +00:00
committed by GitHub
parent 6e6a1034d7
commit f6c6bc2155
68 changed files with 1922 additions and 1585 deletions
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8
cranelift/codegen/src/isa/riscv64/lower.isle
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@@ -328,12 +328,12 @@
(lower_clz_i128 x))
;;;; Rules for `uextend` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(rule (lower (has_type out (uextend x @ (value_type in))))
(lower_extend x $false (ty_bits in) (ty_bits out)))
(rule (lower (has_type out_ty (uextend val @ (value_type in_ty))))
(zext val in_ty out_ty))
;;;; Rules for `sextend` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(rule (lower (has_type out (sextend x @ (value_type in))))
(lower_extend x $true (ty_bits in) (ty_bits out)))
(rule (lower (has_type out_ty (sextend val @ (value_type in_ty))))
(sext val in_ty out_ty))
;;;; Rules for `popcnt` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;