riscv64: Improve signed and zero extend codegen (#5844)

* riscv64: Remove unused code

* riscv64: Group extend rules

* riscv64: Remove more unused rules

* riscv64: Cleanup existing extension rules

* riscv64: Move the existing Extend rules to ISLE

* riscv64: Use `sext.w` when extending

* riscv64: Remove duplicate extend tests

* riscv64: Use `zbb` instructions when extending values

* riscv64: Use `zbkb` extensions when zero extending

* riscv64: Enable additional tests for extend i128

* riscv64: Fix formatting for `Inst::Extend`

* riscv64: Reverse register for pack

* riscv64: Misc Cleanups

* riscv64: Cleanup extend rules

cranelift/codegen/src/isa/riscv64/lower/isle.rs

@@ -229,17 +229,6 @@ impl generated_code::Context for IsleContext<'_, '_, MInst, Riscv64Backend> {
         x as i32
     }
 
-    fn ext_sign_bit(&mut self, ty: Type, r: Reg) -> Reg {
-        assert!(ty.is_int());
-        let rd = self.temp_writable_reg(I64);
-        self.emit(&MInst::AluRRImm12 {
-            alu_op: AluOPRRI::Bexti,
-            rd,
-            rs: r,
-            imm12: Imm12::from_bits((ty.bits() - 1) as i16),
-        });
-        rd.to_reg()
-    }
     fn imm12_const(&mut self, val: i32) -> Imm12 {
         if let Some(res) = Imm12::maybe_from_u64(val as u64) {
             res