riscv64: Improve signed and zero extend codegen (#5844)
* riscv64: Remove unused code * riscv64: Group extend rules * riscv64: Remove more unused rules * riscv64: Cleanup existing extension rules * riscv64: Move the existing Extend rules to ISLE * riscv64: Use `sext.w` when extending * riscv64: Remove duplicate extend tests * riscv64: Use `zbb` instructions when extending values * riscv64: Use `zbkb` extensions when zero extending * riscv64: Enable additional tests for extend i128 * riscv64: Fix formatting for `Inst::Extend` * riscv64: Reverse register for pack * riscv64: Misc Cleanups * riscv64: Cleanup extend rules
This commit is contained in:
Afonso Bordado
@@ -569,6 +569,11 @@
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(Clmul)
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(Clmulh)
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(Clmulr)
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;; Zbkb: Bit-manipulation for Cryptography
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(Pack)
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(Packw)
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(Packh)
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))
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@@ -858,22 +863,6 @@
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(_ Unit (emit (MInst.AluRRImm12 op dst src (imm12_zero)))))
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dst))
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;; extend int if need.
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(decl ext_int_if_need (bool ValueRegs Type) ValueRegs)
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;;; for I8, I16, and I32 ...
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(rule -1
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(ext_int_if_need signed val ty)
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(gen_extend val signed (ty_bits ty) 64))
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;;; otherwise this is a I64 or I128
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;;; no need to extend.
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(rule
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(ext_int_if_need _ r $I64)
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r)
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(rule
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(ext_int_if_need _ r $I128)
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r)
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;; Helper for get negative of Imm12
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(decl neg_imm12 (Imm12) Imm12)
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(extern constructor neg_imm12 neg_imm12)
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@@ -1031,50 +1020,116 @@
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;; add low and high together.
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(result Reg (alu_add high low)))
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(value_regs result (load_u64_constant 0))))
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(decl gen_extend (Reg bool u8 u8) Reg)
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(rule
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(gen_extend r is_signed from_bits to_bits)
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(let
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((tmp WritableReg (temp_writable_reg $I16))
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(_ Unit (emit (MInst.Extend tmp r is_signed from_bits to_bits))))
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tmp))
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;; val is_signed from_bits to_bits
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(decl lower_extend (Reg bool u8 u8) ValueRegs)
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(rule -1
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(lower_extend r is_signed from_bits to_bits)
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(gen_extend r is_signed from_bits to_bits))
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;;;; for I128 signed extend.
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(rule 1
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(lower_extend r $true 64 128)
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(let
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((tmp Reg (alu_rrr (AluOPRRR.Slt) r (zero_reg)))
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(high Reg (gen_extend tmp $true 1 64)))
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(value_regs (gen_move2 r $I64 $I64) high)))
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(rule
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(lower_extend r $true from_bits 128)
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(let
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((tmp Reg (gen_extend r $true from_bits 64))
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(tmp2 Reg (alu_rrr (AluOPRRR.Slt) tmp (zero_reg)))
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(high Reg (gen_extend tmp2 $true 1 64)))
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(value_regs (gen_move2 tmp $I64 $I64) high)))
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;; Extends an integer if it is smaller than 64 bits.
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(decl ext_int_if_need (bool ValueRegs Type) ValueRegs)
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;;; For values smaller than 64 bits, we need to extend them to 64 bits
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(rule 0 (ext_int_if_need $true val (fits_in_32 (ty_int ty)))
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(sext val ty $I64))
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(rule 0 (ext_int_if_need $false val (fits_in_32 (ty_int ty)))
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(zext val ty $I64))
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;; If the value is larger than one machine register, we don't need to do anything
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(rule 1 (ext_int_if_need _ r $I64) r)
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(rule 2 (ext_int_if_need _ r $I128) r)
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;;;; for I128 unsigned extend.
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(rule 1
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(lower_extend r $false 64 128)
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(value_regs (gen_move2 r $I64 $I64) (load_u64_constant 0)))
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;; Performs a zero extension of the given value
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(decl zext (ValueRegs Type Type) ValueRegs)
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(rule (zext val from_ty to_ty) (extend val (ExtendOp.Zero) from_ty to_ty))
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;; Performs a signed extension of the given value
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(decl sext (ValueRegs Type Type) ValueRegs)
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(rule (sext val from_ty to_ty) (extend val (ExtendOp.Signed) from_ty to_ty))
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(type ExtendOp
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(enum
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(Zero)
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(Signed)))
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;; Performs either a sign or zero extension of the given value
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(decl extend (ValueRegs ExtendOp Type Type) ValueRegs)
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;;; Generic Rules Extending to I64
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(decl pure extend_shift_op (ExtendOp) AluOPRRI)
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(rule (extend_shift_op (ExtendOp.Zero)) (AluOPRRI.Srli))
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(rule (extend_shift_op (ExtendOp.Signed)) (AluOPRRI.Srai))
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;; In the most generic case, we shift left and then shift right.
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;; The type of right shift is determined by the extend op.
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(rule 0 (extend val extend_op (fits_in_32 from_ty) (fits_in_64 to_ty))
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(let ((val Reg (value_regs_get val 0))
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(shift Imm12 (imm_from_bits (u64_sub 64 (ty_bits from_ty))))
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(left Reg (alu_rr_imm12 (AluOPRRI.Slli) val shift))
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(shift_op AluOPRRI (extend_shift_op extend_op))
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(right Reg (alu_rr_imm12 shift_op left shift)))
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right))
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;; If we are zero extending a U8 we can use a `andi` instruction.
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(rule 1 (extend val (ExtendOp.Zero) $I8 (fits_in_64 to_ty))
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(let ((val Reg (value_regs_get val 0)))
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(alu_rr_imm12 (AluOPRRI.Andi) val (imm12_const 255))))
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;; When signed extending from 32 to 64 bits we can use a
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;; `addiw val 0`. Also known as a `sext.w`
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(rule 1 (extend val (ExtendOp.Signed) $I32 $I64)
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(let ((val Reg (value_regs_get val 0)))
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(alu_rr_imm12 (AluOPRRI.Addiw) val (imm12_const 0))))
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;; No point in trying to use `packh` here to zero extend 8 bit values
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;; since we can just use `andi` instead which is part of the base ISA.
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;; If we have the `zbkb` extension `packw` can be used to zero extend 16 bit values
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(rule 1 (extend val (ExtendOp.Zero) $I16 (fits_in_64 _))
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(if-let $true (has_zbkb))
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(let ((val Reg (value_regs_get val 0)))
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(alu_rrr (AluOPRRR.Packw) val (zero_reg))))
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;; If we have the `zbkb` extension `pack` can be used to zero extend 32 bit registers
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(rule 1 (extend val (ExtendOp.Zero) $I32 $I64)
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(if-let $true (has_zbkb))
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(let ((val Reg (value_regs_get val 0)))
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(alu_rrr (AluOPRRR.Pack) val (zero_reg))))
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;; If we have the `zbb` extension we can use the dedicated `sext.b` instruction.
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(rule 1 (extend val (ExtendOp.Signed) $I8 (fits_in_64 _))
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(if-let $true (has_zbb))
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(let ((val Reg (value_regs_get val 0)))
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(alu_rr_imm12 (AluOPRRI.Sextb) val (imm12_const 0))))
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;; If we have the `zbb` extension we can use the dedicated `sext.h` instruction.
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(rule 1 (extend val (ExtendOp.Signed) $I16 (fits_in_64 _))
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(if-let $true (has_zbb))
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(let ((val Reg (value_regs_get val 0)))
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(alu_rr_imm12 (AluOPRRI.Sexth) val (imm12_const 0))))
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;; If we have the `zbb` extension we can use the dedicated `zext.h` instruction.
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(rule 2 (extend val (ExtendOp.Zero) $I16 (fits_in_64 _))
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(if-let $true (has_zbb))
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(let ((val Reg (value_regs_get val 0)))
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(alu_rr_imm12 (AluOPRRI.Zexth) val (imm12_const 0))))
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;;; Signed rules extending to I128
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;; Extend the bottom part, and extract the sign bit from the bottom as the top
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(rule 2 (extend val (ExtendOp.Signed) (fits_in_64 from_ty) $I128)
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(let ((val Reg (value_regs_get val 0))
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(low Reg (extend val (ExtendOp.Signed) from_ty $I64))
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(high Reg (alu_rr_imm12 (AluOPRRI.Srai) low (imm12_const 63))))
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(value_regs low high)))
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;;; Unsigned rules extending to I128
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;; Extend the bottom register to I64 and then just zero out the top half.
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(rule 3 (extend val (ExtendOp.Zero) (fits_in_64 from_ty) $I128)
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(let ((val Reg (value_regs_get val 0))
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(low Reg (extend val (ExtendOp.Zero) from_ty $I64))
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(high Reg (load_u64_constant 0)))
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(value_regs low high)))
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;; Catch all rule for ignoring extensions of the same type.
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(rule 4 (extend val _ ty ty) val)
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(rule
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(lower_extend r $false from_bits 128)
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(value_regs (gen_extend r $false from_bits 64) (load_u64_constant 0)))
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;; extract the sign bit of integer.
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(decl ext_sign_bit (Type Reg) Reg)
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(extern constructor ext_sign_bit ext_sign_bit)
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(decl lower_b128_binary (AluOPRRR ValueRegs ValueRegs) ValueRegs)
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(rule
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@@ -1795,50 +1850,6 @@
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(rule (lower_icmp cc x y ty)
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(gen_icmp cc (ext_int_if_need $false x ty) (ext_int_if_need $false y ty) ty))
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(decl lower_icmp_over_flow (ValueRegs ValueRegs Type) Reg)
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;;; for I8 I16 I32
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(rule 1
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(lower_icmp_over_flow x y ty)
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(let
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((tmp Reg (alu_sub (ext_int_if_need $true x ty) (ext_int_if_need $true y ty)))
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(tmp2 WritableReg (temp_writable_reg $I64))
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(_ Unit (emit (MInst.Extend tmp2 tmp $true (ty_bits ty) 64))))
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(gen_icmp (IntCC.NotEqual) (writable_reg_to_reg tmp2) tmp $I64)))
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;;; $I64
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(rule 3
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(lower_icmp_over_flow x y $I64)
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(let
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((y_sign Reg (alu_rrr (AluOPRRR.Sgt) y (zero_reg)))
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(sub_result Reg (alu_sub x y))
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(tmp Reg (alu_rrr (AluOPRRR.Slt) sub_result x)))
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(gen_icmp (IntCC.NotEqual) y_sign tmp $I64)))
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;;; $I128
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(rule 2
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(lower_icmp_over_flow x y $I128)
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(let
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( ;; x sign bit.
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(xs Reg (alu_rr_imm12 (AluOPRRI.Srli) (value_regs_get x 1) (imm12_const 63)))
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;; y sign bit.
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(ys Reg (alu_rr_imm12 (AluOPRRI.Srli) (value_regs_get y 1) (imm12_const 63)))
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;;
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(sub_result ValueRegs (i128_sub x y))
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;; result sign bit.
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(rs Reg (alu_rr_imm12 (AluOPRRI.Srli) (value_regs_get sub_result 1) (imm12_const 63)))
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;;; xs && !ys && !rs
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;;; x is positive y is negtive and result is negative.
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;;; must overflow
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(tmp1 Reg (alu_and xs (alu_and (gen_bit_not ys) (gen_bit_not rs))))
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;;; !xs && ys && rs
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;;; x is negative y is positive and result is positive.
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;;; overflow
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(tmp2 Reg (alu_and (gen_bit_not xs) (alu_and ys rs)))
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;;;tmp3
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(tmp3 Reg (alu_rrr (AluOPRRR.Or) tmp1 tmp2)))
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(gen_extend tmp3 $true 1 64)))
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(decl i128_sub (ValueRegs ValueRegs) ValueRegs)
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(rule
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