arm32 codegen

This commit adds arm32 code generation for some IR insts.
Floating-point instructions are not supported, because regalloc
does not allow to represent overlapping register classes,
which are needed by VFP/Neon.

There is also no support for big-endianness, I64 and I128 types.

cranelift/codegen/src/isa/arm32/mod.rs

@@ -1,149 +1,123 @@
-//! ARM 32-bit Instruction Set Architecture.
+//! 32-bit ARM Instruction Set Architecture.
 
-mod abi;
-mod binemit;
-mod enc_tables;
-mod registers;
-pub mod settings;
-
-use super::super::settings as shared_settings;
-#[cfg(feature = "testing_hooks")]
-use crate::binemit::CodeSink;
-use crate::binemit::{emit_function, MemoryCodeSink};
-use crate::ir;
-use crate::isa::enc_tables::{self as shared_enc_tables, lookup_enclist, Encodings};
+use crate::ir::condcodes::IntCC;
+use crate::ir::Function;
 use crate::isa::Builder as IsaBuilder;
-use crate::isa::{EncInfo, RegClass, RegInfo, TargetIsa};
-use crate::regalloc;
-use alloc::borrow::Cow;
-use alloc::boxed::Box;
-use core::any::Any;
-use core::fmt;
-use target_lexicon::{Architecture, Triple};
+use crate::machinst::{
+    compile, MachBackend, MachCompileResult, ShowWithRRU, TargetIsaAdapter, VCode,
+};
+use crate::result::CodegenResult;
+use crate::settings;
 
-#[allow(dead_code)]
-struct Isa {
+use alloc::boxed::Box;
+use regalloc::RealRegUniverse;
+use target_lexicon::{Architecture, ArmArchitecture, Triple};
+
+// New backend:
+mod abi;
+mod inst;
+mod lower;
+mod lower_inst;
+
+use inst::create_reg_universe;
+
+/// An ARM32 backend.
+pub struct Arm32Backend {
     triple: Triple,
-    shared_flags: shared_settings::Flags,
-    isa_flags: settings::Flags,
-    cpumode: &'static [shared_enc_tables::Level1Entry<u16>],
+    flags: settings::Flags,
+    reg_universe: RealRegUniverse,
 }
 
-/// Get an ISA builder for creating ARM32 targets.
-pub fn isa_builder(triple: Triple) -> IsaBuilder {
-    IsaBuilder {
-        triple,
-        setup: settings::builder(),
-        constructor: isa_constructor,
+impl Arm32Backend {
+    /// Create a new ARM32 backend with the given (shared) flags.
+    pub fn new_with_flags(triple: Triple, flags: settings::Flags) -> Arm32Backend {
+        let reg_universe = create_reg_universe();
+        Arm32Backend {
+            triple,
+            flags,
+            reg_universe,
+        }
+    }
+
+    fn compile_vcode(
+        &self,
+        func: &Function,
+        flags: settings::Flags,
+    ) -> CodegenResult<VCode<inst::Inst>> {
+        // This performs lowering to VCode, register-allocates the code, computes
+        // block layout and finalizes branches. The result is ready for binary emission.
+        let abi = Box::new(abi::Arm32ABICallee::new(func, flags)?);
+        compile::compile::<Arm32Backend>(func, self, abi)
     }
 }
 
-fn isa_constructor(
-    triple: Triple,
-    shared_flags: shared_settings::Flags,
-    builder: shared_settings::Builder,
-) -> Box<dyn TargetIsa> {
-    let level1 = match triple.architecture {
-        Architecture::Arm(arm) => {
-            if arm.is_thumb() {
-                &enc_tables::LEVEL1_T32[..]
-            } else {
-                &enc_tables::LEVEL1_A32[..]
-            }
-        }
-        _ => panic!(),
-    };
-    Box::new(Isa {
-        triple,
-        isa_flags: settings::Flags::new(&shared_flags, builder),
-        shared_flags,
-        cpumode: level1,
-    })
-}
+impl MachBackend for Arm32Backend {
+    fn compile_function(
+        &self,
+        func: &Function,
+        want_disasm: bool,
+    ) -> CodegenResult<MachCompileResult> {
+        let flags = self.flags();
+        let vcode = self.compile_vcode(func, flags.clone())?;
+        let buffer = vcode.emit();
+        let frame_size = vcode.frame_size();
+
+        let disasm = if want_disasm {
+            Some(vcode.show_rru(Some(&create_reg_universe())))
+        } else {
+            None
+        };
+
+        let buffer = buffer.finish();
+
+        Ok(MachCompileResult {
+            buffer,
+            frame_size,
+            disasm,
+        })
+    }
 
-impl TargetIsa for Isa {
     fn name(&self) -> &'static str {
         "arm32"
     }
 
-    fn triple(&self) -> &Triple {
-        &self.triple
+    fn triple(&self) -> Triple {
+        self.triple.clone()
     }
 
-    fn flags(&self) -> &shared_settings::Flags {
-        &self.shared_flags
+    fn flags(&self) -> &settings::Flags {
+        &self.flags
     }
 
-    fn register_info(&self) -> RegInfo {
-        registers::INFO.clone()
+    fn reg_universe(&self) -> &RealRegUniverse {
+        &self.reg_universe
     }
 
-    fn encoding_info(&self) -> EncInfo {
-        enc_tables::INFO.clone()
+    fn unsigned_add_overflow_condition(&self) -> IntCC {
+        // Carry flag set.
+        IntCC::UnsignedGreaterThanOrEqual
     }
 
-    fn legal_encodings<'a>(
-        &'a self,
-        func: &'a ir::Function,
-        inst: &'a ir::InstructionData,
-        ctrl_typevar: ir::Type,
-    ) -> Encodings<'a> {
-        lookup_enclist(
-            ctrl_typevar,
-            inst,
-            func,
-            self.cpumode,
-            &enc_tables::LEVEL2[..],
-            &enc_tables::ENCLISTS[..],
-            &enc_tables::LEGALIZE_ACTIONS[..],
-            &enc_tables::RECIPE_PREDICATES[..],
-            &enc_tables::INST_PREDICATES[..],
-            self.isa_flags.predicate_view(),
-        )
-    }
-
-    fn legalize_signature(&self, sig: &mut Cow<ir::Signature>, current: bool) {
-        abi::legalize_signature(sig, &self.triple, current)
-    }
-
-    fn regclass_for_abi_type(&self, ty: ir::Type) -> RegClass {
-        abi::regclass_for_abi_type(ty)
-    }
-
-    fn allocatable_registers(&self, func: &ir::Function) -> regalloc::RegisterSet {
-        abi::allocatable_registers(func)
-    }
-
-    #[cfg(feature = "testing_hooks")]
-    fn emit_inst(
-        &self,
-        func: &ir::Function,
-        inst: ir::Inst,
-        divert: &mut regalloc::RegDiversions,
-        sink: &mut dyn CodeSink,
-    ) {
-        binemit::emit_inst(func, inst, divert, sink, self)
-    }
-
-    fn emit_function_to_memory(&self, func: &ir::Function, sink: &mut MemoryCodeSink) {
-        emit_function(func, binemit::emit_inst, sink, self)
-    }
-
-    fn unsigned_add_overflow_condition(&self) -> ir::condcodes::IntCC {
-        ir::condcodes::IntCC::UnsignedLessThan
-    }
-
-    fn unsigned_sub_overflow_condition(&self) -> ir::condcodes::IntCC {
-        ir::condcodes::IntCC::UnsignedGreaterThanOrEqual
-    }
-
-    fn as_any(&self) -> &dyn Any {
-        self as &dyn Any
+    fn unsigned_sub_overflow_condition(&self) -> IntCC {
+        // Carry flag clear.
+        IntCC::UnsignedLessThan
     }
 }
 
-impl fmt::Display for Isa {
-    fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
-        write!(f, "{}\n{}", self.shared_flags, self.isa_flags)
+/// Create a new `isa::Builder`.
+pub fn isa_builder(triple: Triple) -> IsaBuilder {
+    assert!(match triple.architecture {
+        Architecture::Arm(ArmArchitecture::Arm)
+        | Architecture::Arm(ArmArchitecture::Armv7)
+        | Architecture::Arm(ArmArchitecture::Armv6) => true,
+        _ => false,
+    });
+    IsaBuilder {
+        triple,
+        setup: settings::builder(),
+        constructor: |triple, shared_flags, _| {
+            let backend = Arm32Backend::new_with_flags(triple, shared_flags);
+            Box::new(TargetIsaAdapter::new(backend))
+        },
     }
 }