arm32 codegen
This commit adds arm32 code generation for some IR insts. Floating-point instructions are not supported, because regalloc does not allow to represent overlapping register classes, which are needed by VFP/Neon. There is also no support for big-endianness, I64 and I128 types.
This commit is contained in:
Jakub Krauz
623
cranelift/codegen/src/isa/arm32/lower_inst.rs
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623
cranelift/codegen/src/isa/arm32/lower_inst.rs
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@@ -0,0 +1,623 @@
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//! Lower a single Cranelift instruction into vcode.
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use crate::ir::types::*;
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use crate::ir::Inst as IRInst;
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use crate::ir::Opcode;
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use crate::machinst::lower::*;
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use crate::machinst::*;
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use crate::CodegenResult;
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use crate::isa::arm32::abi::*;
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use crate::isa::arm32::inst::*;
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use regalloc::RegClass;
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use smallvec::SmallVec;
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use super::lower::*;
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/// Actually codegen an instruction's results into registers.
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pub(crate) fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
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ctx: &mut C,
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insn: IRInst,
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) -> CodegenResult<()> {
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let op = ctx.data(insn).opcode();
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let inputs: SmallVec<[InsnInput; 4]> = (0..ctx.num_inputs(insn))
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.map(|i| InsnInput { insn, input: i })
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.collect();
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let outputs: SmallVec<[InsnOutput; 2]> = (0..ctx.num_outputs(insn))
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.map(|i| InsnOutput { insn, output: i })
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.collect();
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let ty = if outputs.len() > 0 {
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let ty = ctx.output_ty(insn, 0);
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if ty.bits() > 32 || ty.is_float() {
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panic!("Cannot lower inst with type {}!", ty);
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}
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Some(ty)
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} else {
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None
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};
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match op {
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Opcode::Iconst | Opcode::Bconst | Opcode::Null => {
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let value = output_to_const(ctx, outputs[0]).unwrap();
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let rd = output_to_reg(ctx, outputs[0]);
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lower_constant(ctx, rd, value);
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}
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Opcode::Iadd
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| Opcode::IaddIfcin
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| Opcode::IaddIfcout
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| Opcode::IaddIfcarry
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| Opcode::Isub
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| Opcode::IsubIfbin
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| Opcode::IsubIfbout
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| Opcode::IsubIfborrow
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| Opcode::Band
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| Opcode::Bor
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| Opcode::Bxor
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| Opcode::BandNot
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| Opcode::BorNot => {
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let rd = output_to_reg(ctx, outputs[0]);
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let rn = input_to_reg(ctx, inputs[0], NarrowValueMode::None);
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let rm = input_to_reg(ctx, inputs[1], NarrowValueMode::None);
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let alu_op = match op {
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Opcode::Iadd => ALUOp::Add,
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Opcode::IaddIfcin => ALUOp::Adc,
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Opcode::IaddIfcout => ALUOp::Adds,
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Opcode::IaddIfcarry => ALUOp::Adcs,
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Opcode::Isub => ALUOp::Sub,
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Opcode::IsubIfbin => ALUOp::Sbc,
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Opcode::IsubIfbout => ALUOp::Subs,
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Opcode::IsubIfborrow => ALUOp::Sbcs,
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Opcode::Band => ALUOp::And,
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Opcode::Bor => ALUOp::Orr,
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Opcode::Bxor => ALUOp::Eor,
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Opcode::BandNot => ALUOp::Bic,
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Opcode::BorNot => ALUOp::Orn,
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_ => unreachable!(),
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};
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ctx.emit(Inst::AluRRRShift {
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alu_op,
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rd,
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rn,
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rm,
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shift: None,
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});
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}
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Opcode::SaddSat | Opcode::SsubSat | Opcode::Imul | Opcode::Udiv | Opcode::Sdiv => {
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let rd = output_to_reg(ctx, outputs[0]);
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let rn = input_to_reg(ctx, inputs[0], NarrowValueMode::None);
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let rm = input_to_reg(ctx, inputs[1], NarrowValueMode::None);
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let alu_op = match op {
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Opcode::SaddSat => ALUOp::Qadd,
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Opcode::SsubSat => ALUOp::Qsub,
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Opcode::Imul => ALUOp::Mul,
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Opcode::Udiv => ALUOp::Udiv,
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Opcode::Sdiv => ALUOp::Sdiv,
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_ => unreachable!(),
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};
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ctx.emit(Inst::AluRRR { alu_op, rd, rn, rm });
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}
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Opcode::Ineg => {
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let rd = output_to_reg(ctx, outputs[0]);
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let rn = input_to_reg(ctx, inputs[0], NarrowValueMode::None);
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ctx.emit(Inst::AluRRImm8 {
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alu_op: ALUOp::Rsb,
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rd,
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rn,
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imm8: UImm8::maybe_from_i64(0).unwrap(),
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});
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}
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Opcode::Ishl | Opcode::Ushr | Opcode::Sshr => {
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let (alu_op, ext) = match op {
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Opcode::Ishl => (ALUOp::Lsl, NarrowValueMode::None),
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Opcode::Ushr => (ALUOp::Lsr, NarrowValueMode::ZeroExtend),
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Opcode::Sshr => (ALUOp::Asr, NarrowValueMode::SignExtend),
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_ => unreachable!(),
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};
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let rd = output_to_reg(ctx, outputs[0]);
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let rn = input_to_reg(ctx, inputs[0], ext);
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let rm = input_to_reg(ctx, inputs[1], NarrowValueMode::ZeroExtend);
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ctx.emit(Inst::AluRRR { alu_op, rd, rn, rm });
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}
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Opcode::Rotr => {
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if ty.unwrap().bits() != 32 {
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unimplemented!()
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}
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let rd = output_to_reg(ctx, outputs[0]);
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let rn = input_to_reg(ctx, inputs[0], NarrowValueMode::None);
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let rm = input_to_reg(ctx, inputs[1], NarrowValueMode::None);
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ctx.emit(Inst::AluRRR {
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alu_op: ALUOp::Ror,
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rd,
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rn,
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rm,
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});
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}
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Opcode::Rotl => {
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if ty.unwrap().bits() != 32 {
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unimplemented!()
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}
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let rd = output_to_reg(ctx, outputs[0]);
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let rn = input_to_reg(ctx, inputs[0], NarrowValueMode::None);
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let rm = input_to_reg(ctx, inputs[1], NarrowValueMode::None);
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let tmp = ctx.alloc_tmp(RegClass::I32, I32);
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// ror rd, rn, 32 - (rm & 31)
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ctx.emit(Inst::AluRRImm8 {
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alu_op: ALUOp::And,
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rd: tmp,
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rn: rm,
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imm8: UImm8::maybe_from_i64(31).unwrap(),
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});
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ctx.emit(Inst::AluRRImm8 {
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alu_op: ALUOp::Rsb,
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rd: tmp,
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rn: tmp.to_reg(),
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imm8: UImm8::maybe_from_i64(32).unwrap(),
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});
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ctx.emit(Inst::AluRRR {
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alu_op: ALUOp::Ror,
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rd,
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rn,
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rm: tmp.to_reg(),
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});
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}
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Opcode::Smulhi | Opcode::Umulhi => {
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let ty = ty.unwrap();
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let is_signed = op == Opcode::Smulhi;
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match ty {
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I32 => {
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let rd_hi = output_to_reg(ctx, outputs[0]);
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let rd_lo = ctx.alloc_tmp(RegClass::I32, ty);
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let rn = input_to_reg(ctx, inputs[0], NarrowValueMode::None);
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let rm = input_to_reg(ctx, inputs[1], NarrowValueMode::None);
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let alu_op = if is_signed {
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ALUOp::Smull
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} else {
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ALUOp::Umull
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};
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ctx.emit(Inst::AluRRRR {
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alu_op,
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rd_hi,
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rd_lo,
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rn,
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rm,
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});
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}
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I16 | I8 => {
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let narrow_mode = if is_signed {
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NarrowValueMode::SignExtend
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} else {
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NarrowValueMode::ZeroExtend
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};
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let rd = output_to_reg(ctx, outputs[0]);
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let rn = input_to_reg(ctx, inputs[0], narrow_mode);
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let rm = input_to_reg(ctx, inputs[1], narrow_mode);
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ctx.emit(Inst::AluRRR {
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alu_op: ALUOp::Mul,
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rd,
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rn,
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rm,
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});
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let shift_amt = if ty == I16 { 16 } else { 8 };
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let imm8 = UImm8::maybe_from_i64(shift_amt).unwrap();
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let alu_op = if is_signed { ALUOp::Asr } else { ALUOp::Lsr };
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ctx.emit(Inst::AluRRImm8 {
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alu_op,
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rd,
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rn: rd.to_reg(),
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imm8,
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});
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}
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_ => panic!("Unexpected type {} in lower {}!", ty, op),
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}
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}
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Opcode::Bnot => {
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let rd = output_to_reg(ctx, outputs[0]);
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let rm = input_to_reg(ctx, inputs[0], NarrowValueMode::None);
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ctx.emit(Inst::AluRRShift {
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alu_op: ALUOp1::Mvn,
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rd,
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rm,
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shift: None,
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});
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}
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Opcode::Clz | Opcode::Ctz => {
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let rd = output_to_reg(ctx, outputs[0]);
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let rm = input_to_reg(ctx, inputs[0], NarrowValueMode::ZeroExtend);
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let ty = ctx.output_ty(insn, 0);
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let in_reg = if op == Opcode::Ctz {
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ctx.emit(Inst::BitOpRR {
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bit_op: BitOp::Rbit,
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rd,
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rm,
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});
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rd.to_reg()
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} else {
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rm
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};
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ctx.emit(Inst::BitOpRR {
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bit_op: BitOp::Clz,
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rd,
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rm: in_reg,
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});
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if ty.bits() < 32 {
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let imm12 = UImm12::maybe_from_i64(32 - ty.bits() as i64).unwrap();
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ctx.emit(Inst::AluRRImm12 {
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alu_op: ALUOp::Sub,
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rd,
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rn: rd.to_reg(),
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imm12,
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});
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}
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}
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Opcode::Bitrev => {
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let rd = output_to_reg(ctx, outputs[0]);
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let rm = input_to_reg(ctx, inputs[0], NarrowValueMode::None);
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let ty = ctx.output_ty(insn, 0);
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let bit_op = BitOp::Rbit;
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match ty.bits() {
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32 => ctx.emit(Inst::BitOpRR { bit_op, rd, rm }),
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n if n < 32 => {
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let shift = ShiftOpAndAmt::new(
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ShiftOp::LSL,
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ShiftOpShiftImm::maybe_from_shift(32 - n as u32).unwrap(),
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);
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ctx.emit(Inst::AluRRShift {
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alu_op: ALUOp1::Mov,
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rd,
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rm,
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shift: Some(shift),
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});
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ctx.emit(Inst::BitOpRR {
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bit_op,
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rd,
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rm: rd.to_reg(),
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});
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}
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_ => panic!("Unexpected output type {}", ty),
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}
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}
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Opcode::Icmp | Opcode::Ifcmp => {
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let condcode = inst_condcode(ctx.data(insn)).unwrap();
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let cond = lower_condcode(condcode);
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let is_signed = condcode_is_signed(condcode);
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let narrow_mode = if is_signed {
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NarrowValueMode::SignExtend
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} else {
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NarrowValueMode::ZeroExtend
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};
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let rd = output_to_reg(ctx, outputs[0]);
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let rn = input_to_reg(ctx, inputs[0], narrow_mode);
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let rm = input_to_reg(ctx, inputs[1], narrow_mode);
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ctx.emit(Inst::Cmp { rn, rm });
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if op == Opcode::Icmp {
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let mut it_insts = vec![];
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it_insts.push(CondInst::new(Inst::MovImm16 { rd, imm16: 1 }, true));
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it_insts.push(CondInst::new(Inst::MovImm16 { rd, imm16: 0 }, false));
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ctx.emit(Inst::It {
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cond,
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insts: it_insts,
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});
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}
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}
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Opcode::Trueif => {
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let cmp_insn = ctx
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.get_input(inputs[0].insn, inputs[0].input)
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.inst
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.unwrap()
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.0;
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debug_assert_eq!(ctx.data(cmp_insn).opcode(), Opcode::Ifcmp);
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emit_cmp(ctx, cmp_insn);
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let condcode = inst_condcode(ctx.data(insn)).unwrap();
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let cond = lower_condcode(condcode);
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let rd = output_to_reg(ctx, outputs[0]);
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let mut it_insts = vec![];
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it_insts.push(CondInst::new(Inst::MovImm16 { rd, imm16: 1 }, true));
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it_insts.push(CondInst::new(Inst::MovImm16 { rd, imm16: 0 }, false));
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ctx.emit(Inst::It {
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cond,
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insts: it_insts,
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});
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}
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Opcode::Select | Opcode::Selectif => {
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let cond = if op == Opcode::Select {
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let rn = input_to_reg(ctx, inputs[0], NarrowValueMode::ZeroExtend);
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ctx.emit(Inst::CmpImm8 { rn, imm8: 0 });
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Cond::Ne
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} else {
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// Verification ensures that the input is always a single-def ifcmp.
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let cmp_insn = ctx
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.get_input(inputs[0].insn, inputs[0].input)
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.inst
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.unwrap()
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.0;
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debug_assert_eq!(ctx.data(cmp_insn).opcode(), Opcode::Ifcmp);
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emit_cmp(ctx, cmp_insn);
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let condcode = inst_condcode(ctx.data(insn)).unwrap();
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lower_condcode(condcode)
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};
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let r1 = input_to_reg(ctx, inputs[1], NarrowValueMode::None);
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let r2 = input_to_reg(ctx, inputs[2], NarrowValueMode::None);
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let out_reg = output_to_reg(ctx, outputs[0]);
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let mut it_insts = vec![];
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it_insts.push(CondInst::new(Inst::mov(out_reg, r1), true));
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it_insts.push(CondInst::new(Inst::mov(out_reg, r2), false));
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ctx.emit(Inst::It {
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cond,
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insts: it_insts,
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});
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}
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Opcode::Store | Opcode::Istore8 | Opcode::Istore16 | Opcode::Istore32 => {
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let off = ldst_offset(ctx.data(insn)).unwrap();
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let elem_ty = match op {
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Opcode::Istore8 => I8,
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Opcode::Istore16 => I16,
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Opcode::Istore32 => I32,
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Opcode::Store => ctx.input_ty(insn, 0),
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_ => unreachable!(),
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};
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if elem_ty.bits() > 32 {
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unimplemented!()
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}
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let bits = elem_ty.bits() as u8;
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assert_eq!(inputs.len(), 2, "only one input for store memory operands");
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let rt = input_to_reg(ctx, inputs[0], NarrowValueMode::None);
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let base = input_to_reg(ctx, inputs[1], NarrowValueMode::None);
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let mem = AMode::RegOffset(base, i64::from(off));
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let memflags = ctx.memflags(insn).expect("memory flags");
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let srcloc = if !memflags.notrap() {
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Some(ctx.srcloc(insn))
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} else {
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None
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};
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ctx.emit(Inst::Store {
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rt,
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mem,
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srcloc,
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bits,
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});
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}
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Opcode::Load
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| Opcode::Uload8
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| Opcode::Sload8
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| Opcode::Uload16
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| Opcode::Sload16
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| Opcode::Uload32
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| Opcode::Sload32 => {
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let off = ldst_offset(ctx.data(insn)).unwrap();
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let elem_ty = match op {
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Opcode::Sload8 | Opcode::Uload8 => I8,
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Opcode::Sload16 | Opcode::Uload16 => I16,
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Opcode::Sload32 | Opcode::Uload32 => I32,
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Opcode::Load => ctx.output_ty(insn, 0),
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_ => unreachable!(),
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};
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if elem_ty.bits() > 32 {
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unimplemented!()
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}
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let bits = elem_ty.bits() as u8;
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let sign_extend = match op {
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Opcode::Sload8 | Opcode::Sload16 | Opcode::Sload32 => true,
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_ => false,
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};
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let out_reg = output_to_reg(ctx, outputs[0]);
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assert_eq!(inputs.len(), 2, "only one input for store memory operands");
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let base = input_to_reg(ctx, inputs[1], NarrowValueMode::None);
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let mem = AMode::RegOffset(base, i64::from(off));
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let memflags = ctx.memflags(insn).expect("memory flags");
|
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let srcloc = if !memflags.notrap() {
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Some(ctx.srcloc(insn))
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} else {
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None
|
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};
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ctx.emit(Inst::Load {
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rt: out_reg,
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mem,
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srcloc,
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bits,
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sign_extend,
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});
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}
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Opcode::Uextend | Opcode::Sextend => {
|
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let output_ty = ty.unwrap();
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let input_ty = ctx.input_ty(insn, 0);
|
||||
let from_bits = input_ty.bits() as u8;
|
||||
let to_bits = 32;
|
||||
let signed = op == Opcode::Sextend;
|
||||
|
||||
let rm = input_to_reg(ctx, inputs[0], NarrowValueMode::None);
|
||||
let rd = output_to_reg(ctx, outputs[0]);
|
||||
|
||||
if output_ty.bits() > 32 {
|
||||
panic!("Unexpected output type {}", output_ty);
|
||||
}
|
||||
if from_bits < to_bits {
|
||||
ctx.emit(Inst::Extend {
|
||||
rd,
|
||||
rm,
|
||||
from_bits,
|
||||
signed,
|
||||
});
|
||||
}
|
||||
}
|
||||
Opcode::Bint | Opcode::Breduce | Opcode::Bextend | Opcode::Ireduce => {
|
||||
let rn = input_to_reg(ctx, inputs[0], NarrowValueMode::ZeroExtend);
|
||||
let rd = output_to_reg(ctx, outputs[0]);
|
||||
let ty = ctx.input_ty(insn, 0);
|
||||
|
||||
ctx.emit(Inst::gen_move(rd, rn, ty));
|
||||
}
|
||||
Opcode::Copy => {
|
||||
let rd = output_to_reg(ctx, outputs[0]);
|
||||
let rn = input_to_reg(ctx, inputs[0], NarrowValueMode::None);
|
||||
let ty = ctx.input_ty(insn, 0);
|
||||
|
||||
ctx.emit(Inst::gen_move(rd, rn, ty));
|
||||
}
|
||||
Opcode::Debugtrap => {
|
||||
ctx.emit(Inst::Bkpt);
|
||||
}
|
||||
Opcode::Trap => {
|
||||
let trap_info = (ctx.srcloc(insn), inst_trapcode(ctx.data(insn)).unwrap());
|
||||
ctx.emit(Inst::Udf { trap_info })
|
||||
}
|
||||
Opcode::Trapif => {
|
||||
let cmp_insn = ctx
|
||||
.get_input(inputs[0].insn, inputs[0].input)
|
||||
.inst
|
||||
.unwrap()
|
||||
.0;
|
||||
debug_assert_eq!(ctx.data(cmp_insn).opcode(), Opcode::Ifcmp);
|
||||
emit_cmp(ctx, cmp_insn);
|
||||
|
||||
let trap_info = (ctx.srcloc(insn), inst_trapcode(ctx.data(insn)).unwrap());
|
||||
let condcode = inst_condcode(ctx.data(insn)).unwrap();
|
||||
let cond = lower_condcode(condcode);
|
||||
|
||||
ctx.emit(Inst::TrapIf { cond, trap_info });
|
||||
}
|
||||
Opcode::FallthroughReturn | Opcode::Return => {
|
||||
for (i, input) in inputs.iter().enumerate() {
|
||||
let reg = input_to_reg(ctx, *input, NarrowValueMode::None);
|
||||
let retval_reg = ctx.retval(i);
|
||||
let ty = ctx.input_ty(insn, i);
|
||||
|
||||
ctx.emit(Inst::gen_move(retval_reg, reg, ty));
|
||||
}
|
||||
}
|
||||
Opcode::Call | Opcode::CallIndirect => {
|
||||
let loc = ctx.srcloc(insn);
|
||||
let (mut abi, inputs) = match op {
|
||||
Opcode::Call => {
|
||||
let (extname, dist) = ctx.call_target(insn).unwrap();
|
||||
let extname = extname.clone();
|
||||
let sig = ctx.call_sig(insn).unwrap();
|
||||
assert_eq!(inputs.len(), sig.params.len());
|
||||
assert_eq!(outputs.len(), sig.returns.len());
|
||||
(
|
||||
Arm32ABICaller::from_func(sig, &extname, dist, loc)?,
|
||||
&inputs[..],
|
||||
)
|
||||
}
|
||||
Opcode::CallIndirect => {
|
||||
let ptr = input_to_reg(ctx, inputs[0], NarrowValueMode::ZeroExtend);
|
||||
let sig = ctx.call_sig(insn).unwrap();
|
||||
assert_eq!(inputs.len() - 1, sig.params.len());
|
||||
assert_eq!(outputs.len(), sig.returns.len());
|
||||
(Arm32ABICaller::from_ptr(sig, ptr, loc, op)?, &inputs[1..])
|
||||
}
|
||||
_ => unreachable!(),
|
||||
};
|
||||
assert_eq!(inputs.len(), abi.num_args());
|
||||
for (i, input) in inputs.iter().enumerate().filter(|(i, _)| *i <= 3) {
|
||||
let arg_reg = input_to_reg(ctx, *input, NarrowValueMode::None);
|
||||
abi.emit_copy_reg_to_arg(ctx, i, arg_reg);
|
||||
}
|
||||
abi.emit_call(ctx);
|
||||
for (i, output) in outputs.iter().enumerate() {
|
||||
let retval_reg = output_to_reg(ctx, *output);
|
||||
abi.emit_copy_retval_to_reg(ctx, i, retval_reg);
|
||||
}
|
||||
}
|
||||
_ => panic!("lowering {} unimplemented!", op),
|
||||
}
|
||||
|
||||
Ok(())
|
||||
}
|
||||
|
||||
pub(crate) fn lower_branch<C: LowerCtx<I = Inst>>(
|
||||
ctx: &mut C,
|
||||
branches: &[IRInst],
|
||||
targets: &[MachLabel],
|
||||
fallthrough: Option<MachLabel>,
|
||||
) -> CodegenResult<()> {
|
||||
// A block should end with at most two branches. The first may be a
|
||||
// conditional branch; a conditional branch can be followed only by an
|
||||
// unconditional branch or fallthrough. Otherwise, if only one branch,
|
||||
// it may be an unconditional branch, a fallthrough, a return, or a
|
||||
// trap. These conditions are verified by `is_ebb_basic()` during the
|
||||
// verifier pass.
|
||||
assert!(branches.len() <= 2);
|
||||
|
||||
if branches.len() == 2 {
|
||||
// Must be a conditional branch followed by an unconditional branch.
|
||||
let op0 = ctx.data(branches[0]).opcode();
|
||||
let op1 = ctx.data(branches[1]).opcode();
|
||||
|
||||
assert!(op1 == Opcode::Jump || op1 == Opcode::Fallthrough);
|
||||
let taken = BranchTarget::Label(targets[0]);
|
||||
let not_taken = match op1 {
|
||||
Opcode::Jump => BranchTarget::Label(targets[1]),
|
||||
Opcode::Fallthrough => BranchTarget::Label(fallthrough.unwrap()),
|
||||
_ => unreachable!(), // assert above.
|
||||
};
|
||||
match op0 {
|
||||
Opcode::Brz | Opcode::Brnz => {
|
||||
let rn = input_to_reg(
|
||||
ctx,
|
||||
InsnInput {
|
||||
insn: branches[0],
|
||||
input: 0,
|
||||
},
|
||||
NarrowValueMode::ZeroExtend,
|
||||
);
|
||||
let cond = if op0 == Opcode::Brz {
|
||||
Cond::Eq
|
||||
} else {
|
||||
Cond::Ne
|
||||
};
|
||||
|
||||
ctx.emit(Inst::CmpImm8 { rn, imm8: 0 });
|
||||
ctx.emit(Inst::CondBr {
|
||||
taken,
|
||||
not_taken,
|
||||
cond,
|
||||
});
|
||||
}
|
||||
_ => unimplemented!(),
|
||||
}
|
||||
} else {
|
||||
// Must be an unconditional branch or an indirect branch.
|
||||
let op = ctx.data(branches[0]).opcode();
|
||||
match op {
|
||||
Opcode::Jump | Opcode::Fallthrough => {
|
||||
assert_eq!(branches.len(), 1);
|
||||
// In the Fallthrough case, the machine-independent driver
|
||||
// fills in `targets[0]` with our fallthrough block, so this
|
||||
// is valid for both Jump and Fallthrough.
|
||||
ctx.emit(Inst::Jump {
|
||||
dest: BranchTarget::Label(targets[0]),
|
||||
});
|
||||
}
|
||||
_ => unimplemented!(),
|
||||
}
|
||||
}
|
||||
|
||||
Ok(())
|
||||
}
|
||||
Reference in New Issue
Block a user