arm32 codegen
This commit adds arm32 code generation for some IR insts. Floating-point instructions are not supported, because regalloc does not allow to represent overlapping register classes, which are needed by VFP/Neon. There is also no support for big-endianness, I64 and I128 types.
This commit is contained in:
Jakub Krauz
240
cranelift/codegen/src/isa/arm32/lower.rs
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240
cranelift/codegen/src/isa/arm32/lower.rs
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//! Lowering rules for 32-bit ARM.
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use crate::ir::condcodes::IntCC;
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use crate::ir::types::*;
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use crate::ir::Inst as IRInst;
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use crate::ir::{InstructionData, Opcode, TrapCode};
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use crate::machinst::lower::*;
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use crate::machinst::*;
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use crate::CodegenResult;
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use crate::isa::arm32::inst::*;
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use crate::isa::arm32::Arm32Backend;
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use super::lower_inst;
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use regalloc::{Reg, RegClass, Writable};
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//============================================================================
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// Lowering: convert instruction outputs to result types.
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/// Lower an instruction output to a 32-bit constant, if possible.
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pub(crate) fn output_to_const<C: LowerCtx<I = Inst>>(ctx: &mut C, out: InsnOutput) -> Option<u64> {
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if out.output > 0 {
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None
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} else {
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let inst_data = ctx.data(out.insn);
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if inst_data.opcode() == Opcode::Null {
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Some(0)
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} else {
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match inst_data {
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&InstructionData::UnaryImm { opcode: _, imm } => {
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// Only has Into for i64; we use u64 elsewhere, so we cast.
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let imm: i64 = imm.into();
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Some(imm as u64)
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}
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&InstructionData::UnaryBool { opcode: _, imm } => Some(u64::from(imm)),
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&InstructionData::UnaryIeee32 { .. } | &InstructionData::UnaryIeee64 { .. } => {
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unimplemented!()
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}
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_ => None,
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}
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}
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}
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}
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/// How to handle narrow values loaded into registers.
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#[derive(Clone, Copy, Debug, PartialEq, Eq)]
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pub(crate) enum NarrowValueMode {
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None,
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/// Zero-extend to 32 bits if original is < 32 bits.
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ZeroExtend,
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/// Sign-extend to 32 bits if original is < 32 bits.
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SignExtend,
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}
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/// Lower an instruction output to a reg.
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pub(crate) fn output_to_reg<C: LowerCtx<I = Inst>>(ctx: &mut C, out: InsnOutput) -> Writable<Reg> {
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ctx.get_output(out.insn, out.output)
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}
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/// Lower an instruction input to a reg.
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///
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/// The given register will be extended appropriately, according to `narrow_mode`.
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pub(crate) fn input_to_reg<C: LowerCtx<I = Inst>>(
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ctx: &mut C,
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input: InsnInput,
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narrow_mode: NarrowValueMode,
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) -> Reg {
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let ty = ctx.input_ty(input.insn, input.input);
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let from_bits = ty.bits() as u8;
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let inputs = ctx.get_input(input.insn, input.input);
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let in_reg = if let Some(c) = inputs.constant {
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let to_reg = ctx.alloc_tmp(Inst::rc_for_type(ty).unwrap(), ty);
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for inst in Inst::gen_constant(to_reg, c, ty, |reg_class, ty| ctx.alloc_tmp(reg_class, ty))
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.into_iter()
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{
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ctx.emit(inst);
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}
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to_reg.to_reg()
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} else {
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ctx.use_input_reg(inputs);
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inputs.reg
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};
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match (narrow_mode, from_bits) {
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(NarrowValueMode::None, _) => in_reg,
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(NarrowValueMode::ZeroExtend, 1) => {
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let tmp = ctx.alloc_tmp(RegClass::I32, I32);
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ctx.emit(Inst::AluRRImm8 {
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alu_op: ALUOp::And,
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rd: tmp,
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rn: in_reg,
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imm8: UImm8::maybe_from_i64(0x1).unwrap(),
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});
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tmp.to_reg()
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}
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(NarrowValueMode::ZeroExtend, n) if n < 32 => {
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let tmp = ctx.alloc_tmp(RegClass::I32, I32);
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ctx.emit(Inst::Extend {
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rd: tmp,
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rm: in_reg,
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signed: false,
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from_bits: n,
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});
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tmp.to_reg()
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}
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(NarrowValueMode::SignExtend, n) if n < 32 => {
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let tmp = ctx.alloc_tmp(RegClass::I32, I32);
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ctx.emit(Inst::Extend {
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rd: tmp,
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rm: in_reg,
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signed: true,
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from_bits: n,
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});
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tmp.to_reg()
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}
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(NarrowValueMode::ZeroExtend, 32) | (NarrowValueMode::SignExtend, 32) => in_reg,
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_ => panic!(
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"Unsupported input width: input ty {} bits {} mode {:?}",
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ty, from_bits, narrow_mode
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),
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}
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}
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pub(crate) fn lower_constant<C: LowerCtx<I = Inst>>(ctx: &mut C, rd: Writable<Reg>, value: u64) {
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// We allow sign bits for high word.
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assert!((value >> 32) == 0x0 || (value >> 32) == (1 << 32) - 1);
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for inst in Inst::load_constant(rd, (value & ((1 << 32) - 1)) as u32) {
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ctx.emit(inst);
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}
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}
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pub(crate) fn emit_cmp<C: LowerCtx<I = Inst>>(ctx: &mut C, insn: IRInst) {
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let inputs = [InsnInput { insn, input: 0 }, InsnInput { insn, input: 1 }];
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let rn = input_to_reg(ctx, inputs[0], NarrowValueMode::None);
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let rm = input_to_reg(ctx, inputs[1], NarrowValueMode::None);
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ctx.emit(Inst::Cmp { rn, rm });
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}
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pub(crate) fn lower_condcode(cc: IntCC) -> Cond {
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match cc {
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IntCC::Equal => Cond::Eq,
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IntCC::NotEqual => Cond::Ne,
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IntCC::SignedGreaterThanOrEqual => Cond::Ge,
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IntCC::SignedGreaterThan => Cond::Gt,
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IntCC::SignedLessThanOrEqual => Cond::Le,
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IntCC::SignedLessThan => Cond::Lt,
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IntCC::UnsignedGreaterThanOrEqual => Cond::Hs,
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IntCC::UnsignedGreaterThan => Cond::Hi,
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IntCC::UnsignedLessThanOrEqual => Cond::Ls,
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IntCC::UnsignedLessThan => Cond::Lo,
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IntCC::Overflow => Cond::Vs,
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IntCC::NotOverflow => Cond::Vc,
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}
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}
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/// Determines whether this condcode interprets inputs as signed or unsigned.
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pub(crate) fn condcode_is_signed(cc: IntCC) -> bool {
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match cc {
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IntCC::Equal => false,
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IntCC::NotEqual => false,
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IntCC::SignedGreaterThanOrEqual => true,
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IntCC::SignedGreaterThan => true,
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IntCC::SignedLessThanOrEqual => true,
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IntCC::SignedLessThan => true,
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IntCC::UnsignedGreaterThanOrEqual => false,
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IntCC::UnsignedGreaterThan => false,
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IntCC::UnsignedLessThanOrEqual => false,
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IntCC::UnsignedLessThan => false,
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IntCC::Overflow => true,
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IntCC::NotOverflow => true,
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}
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}
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//=============================================================================
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// Helpers for instruction lowering.
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pub(crate) fn ldst_offset(data: &InstructionData) -> Option<i32> {
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match data {
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&InstructionData::Load { offset, .. }
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| &InstructionData::StackLoad { offset, .. }
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| &InstructionData::LoadComplex { offset, .. }
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| &InstructionData::Store { offset, .. }
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| &InstructionData::StackStore { offset, .. }
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| &InstructionData::StoreComplex { offset, .. } => Some(offset.into()),
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_ => None,
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}
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}
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pub(crate) fn inst_condcode(data: &InstructionData) -> Option<IntCC> {
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match data {
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&InstructionData::IntCond { cond, .. }
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| &InstructionData::BranchIcmp { cond, .. }
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| &InstructionData::IntCompare { cond, .. }
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| &InstructionData::IntCondTrap { cond, .. }
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| &InstructionData::BranchInt { cond, .. }
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| &InstructionData::IntSelect { cond, .. }
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| &InstructionData::IntCompareImm { cond, .. } => Some(cond),
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_ => None,
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}
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}
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pub(crate) fn inst_trapcode(data: &InstructionData) -> Option<TrapCode> {
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match data {
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&InstructionData::Trap { code, .. }
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| &InstructionData::CondTrap { code, .. }
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| &InstructionData::IntCondTrap { code, .. } => Some(code),
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&InstructionData::FloatCondTrap { code, .. } => {
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panic!("Unexpected float cond trap {:?}", code)
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}
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_ => None,
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}
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}
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//=============================================================================
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// Lowering-backend trait implementation.
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impl LowerBackend for Arm32Backend {
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type MInst = Inst;
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fn lower<C: LowerCtx<I = Inst>>(&self, ctx: &mut C, ir_inst: IRInst) -> CodegenResult<()> {
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lower_inst::lower_insn_to_regs(ctx, ir_inst)
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}
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fn lower_branch_group<C: LowerCtx<I = Inst>>(
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&self,
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ctx: &mut C,
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branches: &[IRInst],
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targets: &[MachLabel],
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fallthrough: Option<MachLabel>,
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) -> CodegenResult<()> {
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lower_inst::lower_branch(ctx, branches, targets, fallthrough)
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}
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fn maybe_pinned_reg(&self) -> Option<Reg> {
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None
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}
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}
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