arm32 codegen
This commit adds arm32 code generation for some IR insts. Floating-point instructions are not supported, because regalloc does not allow to represent overlapping register classes, which are needed by VFP/Neon. There is also no support for big-endianness, I64 and I128 types.
This commit is contained in:
Jakub Krauz
@@ -1,108 +1,450 @@
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//! ARM ABI implementation.
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//! This is from the RISC-V target and will need to be updated for ARM32.
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//! Implementation of the 32-bit ARM ABI.
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use super::registers::{D, GPR, Q, S};
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use crate::abi::{legalize_args, ArgAction, ArgAssigner, ValueConversion};
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use crate::ir::{self, AbiParam, ArgumentExtension, ArgumentLoc, Type};
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use crate::isa::RegClass;
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use crate::regalloc::RegisterSet;
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use alloc::borrow::Cow;
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use core::i32;
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use target_lexicon::Triple;
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use crate::ir;
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use crate::ir::types::*;
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use crate::ir::SourceLoc;
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use crate::isa;
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use crate::isa::arm32::inst::*;
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use crate::machinst::*;
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use crate::settings;
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use crate::{CodegenError, CodegenResult};
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use alloc::boxed::Box;
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use alloc::vec::Vec;
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use regalloc::{RealReg, Reg, RegClass, Set, Writable};
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use smallvec::SmallVec;
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struct Args {
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pointer_bits: u8,
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pointer_bytes: u8,
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pointer_type: Type,
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regs: u32,
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reg_limit: u32,
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offset: u32,
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}
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/// Support for the ARM ABI from the callee side (within a function body).
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pub(crate) type Arm32ABICallee = ABICalleeImpl<Arm32MachineDeps>;
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impl Args {
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fn new(bits: u8) -> Self {
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Self {
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pointer_bits: bits,
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pointer_bytes: bits / 8,
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pointer_type: Type::int(u16::from(bits)).unwrap(),
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regs: 0,
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reg_limit: 8,
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offset: 0,
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/// Support for the ARM ABI from the caller side (at a callsite).
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pub(crate) type Arm32ABICaller = ABICallerImpl<Arm32MachineDeps>;
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/// This is the limit for the size of argument and return-value areas on the
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/// stack. We place a reasonable limit here to avoid integer overflow issues
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/// with 32-bit arithmetic: for now, 128 MB.
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static STACK_ARG_RET_SIZE_LIMIT: u64 = 128 * 1024 * 1024;
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/// ARM-specific ABI behavior. This struct just serves as an implementation
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/// point for the trait; it is never actually instantiated.
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pub(crate) struct Arm32MachineDeps;
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impl Into<AMode> for StackAMode {
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fn into(self) -> AMode {
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match self {
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StackAMode::FPOffset(off, ty) => AMode::FPOffset(off, ty),
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StackAMode::NominalSPOffset(off, ty) => AMode::NominalSPOffset(off, ty),
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StackAMode::SPOffset(off, ty) => AMode::SPOffset(off, ty),
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}
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}
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}
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impl ArgAssigner for Args {
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fn assign(&mut self, arg: &AbiParam) -> ArgAction {
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fn align(value: u32, to: u32) -> u32 {
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(value + to - 1) & !(to - 1)
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}
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impl ABIMachineSpec for Arm32MachineDeps {
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type I = Inst;
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let ty = arg.value_type;
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fn word_bits() -> u32 {
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32
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}
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// Check for a legal type.
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// SIMD instructions are currently no implemented, so break down vectors
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if ty.is_vector() {
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return ValueConversion::VectorSplit.into();
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}
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fn compute_arg_locs(
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_call_conv: isa::CallConv,
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params: &[ir::AbiParam],
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args_or_rets: ArgsOrRets,
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add_ret_area_ptr: bool,
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) -> CodegenResult<(Vec<ABIArg>, i64, Option<usize>)> {
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let mut next_rreg = 0;
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let mut next_stack: u64 = 0;
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let mut ret = vec![];
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let mut stack_args = vec![];
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// Large integers and booleans are broken down to fit in a register.
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if !ty.is_float() && ty.bits() > u16::from(self.pointer_bits) {
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// Align registers and stack to a multiple of two pointers.
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self.regs = align(self.regs, 2);
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self.offset = align(self.offset, 2 * u32::from(self.pointer_bytes));
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return ValueConversion::IntSplit.into();
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}
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let max_reg_val = 4; // r0-r3
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// Small integers are extended to the size of a pointer register.
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if ty.is_int() && ty.bits() < u16::from(self.pointer_bits) {
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match arg.extension {
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ArgumentExtension::None => {}
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ArgumentExtension::Uext => return ValueConversion::Uext(self.pointer_type).into(),
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ArgumentExtension::Sext => return ValueConversion::Sext(self.pointer_type).into(),
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for i in 0..params.len() {
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let param = params[i];
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// Validate "purpose".
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match ¶m.purpose {
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&ir::ArgumentPurpose::VMContext
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| &ir::ArgumentPurpose::Normal
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| &ir::ArgumentPurpose::StackLimit
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| &ir::ArgumentPurpose::SignatureId => {}
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_ => panic!(
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"Unsupported argument purpose {:?} in signature: {:?}",
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param.purpose, params
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),
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}
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assert!(param.value_type.bits() <= 32);
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if next_rreg < max_reg_val {
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let reg = rreg(next_rreg);
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ret.push(ABIArg::Reg(
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reg.to_real_reg(),
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param.value_type,
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param.extension,
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));
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next_rreg += 1;
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} else {
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// Arguments are stored on stack in reversed order.
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// https://static.docs.arm.com/ihi0042/g/aapcs32.pdf
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// Stack offset is not known yet. Store param info for later.
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stack_args.push((param.value_type, param.extension));
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next_stack += 4;
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}
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}
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if self.regs < self.reg_limit {
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// Assign to a register.
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let reg = GPR.unit(10 + self.regs as usize);
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self.regs += 1;
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ArgumentLoc::Reg(reg).into()
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let extra_arg = if add_ret_area_ptr {
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debug_assert!(args_or_rets == ArgsOrRets::Args);
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if next_rreg < max_reg_val {
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ret.push(ABIArg::Reg(
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rreg(next_rreg).to_real_reg(),
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I32,
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ir::ArgumentExtension::None,
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));
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} else {
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stack_args.push((I32, ir::ArgumentExtension::None));
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next_stack += 4;
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}
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Some(ret.len() - 1)
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} else {
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// Assign a stack location.
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let loc = ArgumentLoc::Stack(self.offset as i32);
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self.offset += u32::from(self.pointer_bytes);
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debug_assert!(self.offset <= i32::MAX as u32);
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loc.into()
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None
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};
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// Now we can assign proper stack offsets to params.
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let max_stack = next_stack;
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for (ty, ext) in stack_args.into_iter().rev() {
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next_stack -= 4;
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ret.push(ABIArg::Stack((max_stack - next_stack) as i64, ty, ext));
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}
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assert_eq!(next_stack, 0);
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next_stack = (next_stack + 7) & !7;
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// To avoid overflow issues, limit the arg/return size to something
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// reasonable -- here, 128 MB.
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if next_stack > STACK_ARG_RET_SIZE_LIMIT {
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return Err(CodegenError::ImplLimitExceeded);
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}
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Ok((ret, next_stack as i64, extra_arg))
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}
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fn fp_to_arg_offset(_call_conv: isa::CallConv, _flags: &settings::Flags) -> i64 {
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8 // frame pointer and link register
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}
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fn gen_load_stack(mem: StackAMode, into_reg: Writable<Reg>, ty: Type) -> Inst {
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Inst::gen_load(into_reg, mem.into(), ty)
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}
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fn gen_store_stack(mem: StackAMode, from_reg: Reg, ty: Type) -> Inst {
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Inst::gen_store(from_reg, mem.into(), ty)
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}
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fn gen_move(to_reg: Writable<Reg>, from_reg: Reg, ty: Type) -> Inst {
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Inst::gen_move(to_reg, from_reg, ty)
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}
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fn gen_extend(
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to_reg: Writable<Reg>,
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from_reg: Reg,
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is_signed: bool,
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from_bits: u8,
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to_bits: u8,
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) -> Inst {
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assert!(to_bits == 32);
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assert!(from_bits < 32);
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Inst::Extend {
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rd: to_reg,
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rm: from_reg,
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signed: is_signed,
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from_bits,
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}
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}
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}
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/// Legalize `sig`.
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pub fn legalize_signature(sig: &mut Cow<ir::Signature>, triple: &Triple, _current: bool) {
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let bits = triple.pointer_width().unwrap().bits();
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let mut args = Args::new(bits);
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if let Some(new_params) = legalize_args(&sig.params, &mut args) {
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sig.to_mut().params = new_params;
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fn gen_ret() -> Inst {
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Inst::Ret
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}
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}
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/// Get register class for a type appearing in a legalized signature.
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pub fn regclass_for_abi_type(ty: ir::Type) -> RegClass {
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if ty.is_int() {
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GPR
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} else {
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match ty.bits() {
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32 => S,
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64 => D,
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128 => Q,
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_ => panic!("Unexpected {} ABI type for arm32", ty),
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fn gen_epilogue_placeholder() -> Inst {
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Inst::EpiloguePlaceholder
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}
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fn gen_add_imm(into_reg: Writable<Reg>, from_reg: Reg, imm: u32) -> SmallVec<[Inst; 4]> {
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let mut insts = SmallVec::new();
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if let Some(imm12) = UImm12::maybe_from_i64(imm as i64) {
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insts.push(Inst::AluRRImm12 {
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alu_op: ALUOp::Add,
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rd: into_reg,
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rn: from_reg,
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imm12,
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});
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} else {
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let scratch2 = writable_tmp2_reg();
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insts.extend(Inst::load_constant(scratch2, imm));
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insts.push(Inst::AluRRRShift {
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alu_op: ALUOp::Add,
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rd: into_reg,
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rn: from_reg,
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rm: scratch2.to_reg(),
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shift: None,
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});
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}
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insts
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}
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fn gen_stack_lower_bound_trap(limit_reg: Reg) -> SmallVec<[Inst; 2]> {
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let mut insts = SmallVec::new();
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insts.push(Inst::Cmp {
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rn: sp_reg(),
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rm: limit_reg,
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});
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insts.push(Inst::TrapIf {
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trap_info: (ir::SourceLoc::default(), ir::TrapCode::StackOverflow),
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// Here `Lo` == "less than" when interpreting the two
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// operands as unsigned integers.
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cond: Cond::Lo,
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});
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insts
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}
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fn gen_get_stack_addr(mem: StackAMode, into_reg: Writable<Reg>, _ty: Type) -> Inst {
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let mem = mem.into();
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Inst::LoadAddr { rd: into_reg, mem }
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}
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fn get_stacklimit_reg() -> Reg {
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ip_reg()
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}
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fn gen_load_base_offset(into_reg: Writable<Reg>, base: Reg, offset: i32, ty: Type) -> Inst {
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let mem = AMode::RegOffset(base, offset as i64);
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Inst::gen_load(into_reg, mem, ty)
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}
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fn gen_store_base_offset(base: Reg, offset: i32, from_reg: Reg, ty: Type) -> Inst {
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let mem = AMode::RegOffset(base, offset as i64);
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Inst::gen_store(from_reg, mem, ty)
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}
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fn gen_sp_reg_adjust(amount: i32) -> SmallVec<[Inst; 2]> {
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let mut ret = SmallVec::new();
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if amount == 0 {
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return ret;
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}
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let (amount, is_sub) = if amount > 0 {
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(amount, false)
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} else {
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(-amount, true)
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};
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let alu_op = if is_sub { ALUOp::Sub } else { ALUOp::Add };
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if let Some(imm12) = UImm12::maybe_from_i64(amount as i64) {
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ret.push(Inst::AluRRImm12 {
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alu_op,
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rd: writable_sp_reg(),
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rn: sp_reg(),
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imm12,
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});
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} else {
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let tmp = writable_ip_reg();
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ret.extend(Inst::load_constant(tmp, amount as u32));
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ret.push(Inst::AluRRRShift {
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alu_op,
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rd: writable_sp_reg(),
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rn: sp_reg(),
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rm: tmp.to_reg(),
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shift: None,
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});
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}
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ret
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}
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fn gen_nominal_sp_adj(offset: i32) -> Inst {
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let offset = i64::from(offset);
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Inst::VirtualSPOffsetAdj { offset }
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}
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fn gen_prologue_frame_setup() -> SmallVec<[Inst; 2]> {
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let mut ret = SmallVec::new();
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let reg_list = vec![fp_reg(), lr_reg()];
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ret.push(Inst::Push { reg_list });
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ret.push(Inst::Mov {
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rd: writable_fp_reg(),
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rm: sp_reg(),
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});
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ret
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}
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fn gen_epilogue_frame_restore() -> SmallVec<[Inst; 2]> {
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let mut ret = SmallVec::new();
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ret.push(Inst::Mov {
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rd: writable_sp_reg(),
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rm: fp_reg(),
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});
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let reg_list = vec![writable_fp_reg(), writable_lr_reg()];
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ret.push(Inst::Pop { reg_list });
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ret
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}
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/// Returns stack bytes used as well as instructions. Does not adjust
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/// nominal SP offset; caller will do that.
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fn gen_clobber_save(
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_call_conv: isa::CallConv,
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clobbers: &Set<Writable<RealReg>>,
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) -> (u64, SmallVec<[Inst; 16]>) {
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let mut insts = SmallVec::new();
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let clobbered_vec = get_callee_saves(clobbers);
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let mut clobbered_vec: Vec<_> = clobbered_vec
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.into_iter()
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.map(|r| r.to_reg().to_reg())
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.collect();
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if clobbered_vec.len() % 2 == 1 {
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// For alignment purposes.
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clobbered_vec.push(ip_reg());
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}
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let stack_used = clobbered_vec.len() * 4;
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if !clobbered_vec.is_empty() {
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insts.push(Inst::Push {
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reg_list: clobbered_vec,
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});
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}
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(stack_used as u64, insts)
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}
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fn gen_clobber_restore(
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_call_conv: isa::CallConv,
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clobbers: &Set<Writable<RealReg>>,
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) -> SmallVec<[Inst; 16]> {
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let mut insts = SmallVec::new();
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let clobbered_vec = get_callee_saves(clobbers);
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let mut clobbered_vec: Vec<_> = clobbered_vec
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.into_iter()
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.map(|r| Writable::from_reg(r.to_reg().to_reg()))
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.collect();
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if clobbered_vec.len() % 2 == 1 {
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clobbered_vec.push(writable_ip_reg());
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}
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if !clobbered_vec.is_empty() {
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insts.push(Inst::Pop {
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reg_list: clobbered_vec,
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});
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}
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insts
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}
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fn gen_call(
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dest: &CallDest,
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uses: Vec<Reg>,
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defs: Vec<Writable<Reg>>,
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loc: SourceLoc,
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opcode: ir::Opcode,
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tmp: Writable<Reg>,
|
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) -> SmallVec<[(InstIsSafepoint, Inst); 2]> {
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let mut insts = SmallVec::new();
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match &dest {
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&CallDest::ExtName(ref name, RelocDistance::Near) => insts.push((
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InstIsSafepoint::Yes,
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Inst::Call {
|
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info: Box::new(CallInfo {
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dest: name.clone(),
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uses,
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defs,
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loc,
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opcode,
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}),
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},
|
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)),
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&CallDest::ExtName(ref name, RelocDistance::Far) => {
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insts.push((
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InstIsSafepoint::No,
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Inst::LoadExtName {
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rt: tmp,
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name: Box::new(name.clone()),
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offset: 0,
|
||||
srcloc: loc,
|
||||
},
|
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));
|
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insts.push((
|
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InstIsSafepoint::Yes,
|
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Inst::CallInd {
|
||||
info: Box::new(CallIndInfo {
|
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rm: tmp.to_reg(),
|
||||
uses,
|
||||
defs,
|
||||
loc,
|
||||
opcode,
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||||
}),
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||||
},
|
||||
));
|
||||
}
|
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&CallDest::Reg(reg) => insts.push((
|
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InstIsSafepoint::Yes,
|
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Inst::CallInd {
|
||||
info: Box::new(CallIndInfo {
|
||||
rm: *reg,
|
||||
uses,
|
||||
defs,
|
||||
loc,
|
||||
opcode,
|
||||
}),
|
||||
},
|
||||
)),
|
||||
}
|
||||
|
||||
insts
|
||||
}
|
||||
|
||||
fn get_number_of_spillslots_for_value(rc: RegClass, _ty: Type) -> u32 {
|
||||
match rc {
|
||||
RegClass::I32 => 1,
|
||||
_ => panic!("Unexpected register class!"),
|
||||
}
|
||||
}
|
||||
|
||||
fn get_virtual_sp_offset_from_state(s: &EmitState) -> i64 {
|
||||
s.virtual_sp_offset
|
||||
}
|
||||
|
||||
fn get_nominal_sp_to_fp(s: &EmitState) -> i64 {
|
||||
s.nominal_sp_to_fp
|
||||
}
|
||||
|
||||
fn get_caller_saves(_call_conv: isa::CallConv) -> Vec<Writable<Reg>> {
|
||||
let mut caller_saved = Vec::new();
|
||||
for i in 0..15 {
|
||||
let r = writable_rreg(i);
|
||||
if is_caller_save(r.to_reg().to_real_reg()) {
|
||||
caller_saved.push(r);
|
||||
}
|
||||
}
|
||||
caller_saved
|
||||
}
|
||||
}
|
||||
|
||||
/// Get the set of allocatable registers for `func`.
|
||||
pub fn allocatable_registers(_func: &ir::Function) -> RegisterSet {
|
||||
unimplemented!()
|
||||
fn is_callee_save(r: RealReg) -> bool {
|
||||
let enc = r.get_hw_encoding();
|
||||
4 <= enc && enc <= 10
|
||||
}
|
||||
|
||||
fn get_callee_saves(regs: &Set<Writable<RealReg>>) -> Vec<Writable<RealReg>> {
|
||||
let mut ret = Vec::new();
|
||||
for ® in regs.iter() {
|
||||
if is_callee_save(reg.to_reg()) {
|
||||
ret.push(reg);
|
||||
}
|
||||
}
|
||||
|
||||
// Sort registers for deterministic code output.
|
||||
ret.sort_by_key(|r| r.to_reg().get_index());
|
||||
ret
|
||||
}
|
||||
|
||||
fn is_caller_save(r: RealReg) -> bool {
|
||||
let enc = r.get_hw_encoding();
|
||||
enc <= 3
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user