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load_complex and store_complex instructions (#309)

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* Start adding the load_complex and store_complex instructions.

N.b.:
The text format is not correct yet. Requires changes to the lexer and parser.
I'm not sure why I needed to change the RuntimeError to Exception yet. Will fix.

* Get first few encodings of load_complex working. Still needs var args type checking.

* Clean up ModRM helper functions in binemit.

* Implement 32-bit displace for load_complex

* Use encoding helpers instead of doing them all by hand

* Initial implementation of store_complex

* Parse value list for load/store_complex with + as delimiter. Looks nice.

* Add sign/zero-extension and size variants for load_complex.

* Add size variants of store_complex.

* Add asm helper lines to load/store complex bin tests.

* Example of length-checking the instruction ValueList for an encoding. Extremely questionable implementation.

* Fix Python linting issues

* First draft of postopt pass to fold adds and loads into load_complex. Just simple loads for now.

* Optimization pass now works with all types of loads.

* Add store+add -> store_complex to postopt pass

* Put complex address optimization behind ISA flag.

* Add load/store complex for f32 and f64

* Fixes changes to lexer that broke NaN parsing.

Abstracts away the repeated checks for whether or not the characters
following a + or - are going to be parsed as a number or not.

* Fix formatting issues

* Fix register restrictions for complex addresses.

* Encoding tests for x86-32.

* Add documentation for newly added instructions, recipes, and cdsl changes.

* Fix python formatting again

* Apply value-list length predicates to all LoadComplex and StoreComplex instructions.

* Add predicate types to new encoding helpers for mypy.

* Import FieldPredicate to satisfy mypy.

* Add and fix some "asm" strings in the encoding tests.

* Line-up 'bin' comments in x86/binary64 test

* Test parsing of offset-less store_complex instruction.

* 'sNaN' not 'sNan'

* Bounds check the lookup for polymorphic typevar operand.

* Fix encodings for istore16_complex.
This commit is contained in:
Tyler McMullen
2018-05-09 12:07:00 -07:00
committed by Dan Gohman
parent 5aa84a744b
commit f636d795c5
25 changed files with 1127 additions and 21 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
lib/codegen/src/isa/mod.rs
View File

@@ -162,6 +162,11 @@ pub trait TargetIsa: fmt::Display {
false
}
/// Does the CPU implement multi-register addressing?
fn uses_complex_addresses(&self) -> bool {
false
}
/// Get a data structure describing the registers in this ISA.
fn register_info(&self) -> RegInfo;

36
lib/codegen/src/isa/x86/binemit.rs
View File

@@ -46,6 +46,18 @@ fn rex2(rm: RegUnit, reg: RegUnit) -> u8 {
BASE_REX | b | (r << 2)
}
// Create a three-register REX prefix, setting:
//
// REX.B = bit 3 of r/m register, or SIB base register when a SIB byte is present.
// REX.R = bit 3 of reg register.
// REX.X = bit 3 of SIB index register.
fn rex3(rm: RegUnit, reg: RegUnit, index: RegUnit) -> u8 {
let b = ((rm >> 3) & 1) as u8;
let r = ((reg >> 3) & 1) as u8;
let x = ((index >> 3) & 1) as u8;
BASE_REX | b | (x << 1) | (r << 2)
}
// Emit a REX prefix.
//
// The R, X, and B bits are computed from registers using the functions above. The W bit is
@@ -211,7 +223,19 @@ fn modrm_disp32<CS: CodeSink + ?Sized>(rm: RegUnit, reg: RegUnit, sink: &mut CS)
sink.put1(b);
}
/// Emit a mode 10 ModR/M byte indicating that a SIB byte is present.
/// Emit a mode 00 ModR/M with a 100 RM indicating a SIB byte is present.
fn modrm_sib<CS: CodeSink + ?Sized>(reg: RegUnit, sink: &mut CS) {
modrm_rm(0b100, reg, sink);
}
/// Emit a mode 01 ModR/M with a 100 RM indicating a SIB byte and 8-bit
/// displacement are present.
fn modrm_sib_disp8<CS: CodeSink + ?Sized>(reg: RegUnit, sink: &mut CS) {
modrm_disp8(0b100, reg, sink);
}
/// Emit a mode 10 ModR/M with a 100 RM indicating a SIB byte and 32-bit
/// displacement are present.
fn modrm_sib_disp32<CS: CodeSink + ?Sized>(reg: RegUnit, sink: &mut CS) {
modrm_disp32(0b100, reg, sink);
}
@@ -225,6 +249,16 @@ fn sib_noindex<CS: CodeSink + ?Sized>(base: RegUnit, sink: &mut CS) {
sink.put1(b);
}
fn sib<CS: CodeSink + ?Sized>(scale: u8, index: RegUnit, base: RegUnit, sink: &mut CS) {
// SIB SS_III_BBB.
debug_assert_eq!(scale & !0x03, 0, "Scale out of range");
let scale = scale & 3;
let index = index as u8 & 7;
let base = base as u8 & 7;
let b: u8 = (scale << 6) | (index << 3) | base;
sink.put1(b);
}
/// Get the low 4 bits of an opcode for an integer condition code.
///
/// Add this offset to a base opcode for:

4
lib/codegen/src/isa/x86/mod.rs
View File

@@ -62,6 +62,10 @@ impl TargetIsa for Isa {
true
}
fn uses_complex_addresses(&self) -> bool {
true
}
fn register_info(&self) -> RegInfo {
registers::INFO.clone()
}

160
lib/codegen/src/postopt.rs
View File

@@ -5,9 +5,9 @@
use cursor::{Cursor, EncCursor};
use ir::condcodes::{CondCode, FloatCC, IntCC};
use ir::dfg::ValueDef;
use ir::immediates::Imm64;
use ir::immediates::{Imm64, Offset32};
use ir::instructions::{Opcode, ValueList};
use ir::{Ebb, Function, Inst, InstBuilder, InstructionData, Value};
use ir::{Ebb, Function, Inst, InstBuilder, InstructionData, Value, Type, MemFlags};
use isa::TargetIsa;
use timing;
@@ -173,6 +173,158 @@ fn optimize_cpu_flags(
pos.func.update_encoding(info.br_inst, isa).is_ok();
}
struct MemOpInfo {
opcode: Opcode,
inst: Inst,
itype: Type,
arg: Value,
st_arg: Option<Value>,
flags: MemFlags,
offset: Offset32,
add_args: Option<[Value; 2]>,
}
fn optimize_complex_addresses(pos: &mut EncCursor, inst: Inst, isa: &TargetIsa) {
let mut info = match pos.func.dfg[inst] {
InstructionData::Load {
opcode,
arg,
flags,
offset,
} => MemOpInfo {
opcode: opcode,
inst: inst,
itype: pos.func.dfg.ctrl_typevar(inst),
arg: arg,
st_arg: None,
flags: flags,
offset: offset,
add_args: None,
},
InstructionData::Store {
opcode,
args,
flags,
offset,
} => MemOpInfo {
opcode: opcode,
inst: inst,
itype: pos.func.dfg.ctrl_typevar(inst),
arg: args[1],
st_arg: Some(args[0]),
flags: flags,
offset: offset,
add_args: None,
},
_ => return,
};
if let ValueDef::Result(result_inst, _) = pos.func.dfg.value_def(info.arg) {
match pos.func.dfg[result_inst] {
InstructionData::Binary { opcode, args } if opcode == Opcode::Iadd => {
info.add_args = Some(args.clone());
}
_ => return,
}
} else {
return;
}
match info.opcode {
Opcode::Load => {
pos.func.dfg.replace(info.inst).load_complex(
info.itype,
info.flags,
&info.add_args.unwrap(),
info.offset,
);
}
Opcode::Uload8 => {
pos.func.dfg.replace(info.inst).uload8_complex(
info.itype,
info.flags,
&info.add_args.unwrap(),
info.offset,
);
}
Opcode::Sload8 => {
pos.func.dfg.replace(info.inst).sload8_complex(
info.itype,
info.flags,
&info.add_args.unwrap(),
info.offset,
);
}
Opcode::Uload16 => {
pos.func.dfg.replace(info.inst).uload16_complex(
info.itype,
info.flags,
&info.add_args.unwrap(),
info.offset,
);
}
Opcode::Sload16 => {
pos.func.dfg.replace(info.inst).sload16_complex(
info.itype,
info.flags,
&info.add_args.unwrap(),
info.offset,
);
}
Opcode::Uload32 => {
pos.func.dfg.replace(info.inst).uload32_complex(
info.flags,
&info.add_args.unwrap(),
info.offset,
);
}
Opcode::Sload32 => {
pos.func.dfg.replace(info.inst).sload32_complex(
info.flags,
&info.add_args.unwrap(),
info.offset,
);
}
Opcode::Store => {
pos.func.dfg.replace(info.inst).store_complex(
info.flags,
info.st_arg.unwrap(),
&info.add_args.unwrap(),
info.offset,
);
}
Opcode::Istore8 => {
pos.func.dfg.replace(info.inst).istore8_complex(
info.flags,
info.st_arg.unwrap(),
&info.add_args.unwrap(),
info.offset,
);
}
Opcode::Istore16 => {
pos.func.dfg.replace(info.inst).istore16_complex(
info.flags,
info.st_arg.unwrap(),
&info.add_args.unwrap(),
info.offset,
);
}
Opcode::Istore32 => {
pos.func.dfg.replace(info.inst).istore32_complex(
info.flags,
info.st_arg.unwrap(),
&info.add_args.unwrap(),
info.offset,
);
}
_ => return,
}
pos.func.update_encoding(info.inst, isa).is_ok();
}
//----------------------------------------------------------------------
//
// The main post-opt pass.
@@ -198,6 +350,10 @@ pub fn do_postopt(func: &mut Function, isa: &TargetIsa) {
}
}
}
if isa.uses_complex_addresses() {
optimize_complex_addresses(&mut pos, inst, isa);
}
}
}
}

5
lib/codegen/src/predicates.rs
View File

@@ -46,6 +46,11 @@ pub fn is_colocated_data(global_var: ir::GlobalVar, func: &ir::Function) -> bool
}
}
#[allow(dead_code)]
pub fn has_length_of(value_list: &ir::ValueList, num: usize, func: &ir::Function) -> bool {
value_list.len(&func.dfg.value_lists) == num
}
#[cfg(test)]
mod tests {
use super::*;

8
lib/codegen/src/verifier/mod.rs
View File

@@ -335,6 +335,12 @@ impl<'a> Verifier<'a> {
RegFill { src, .. } => {
self.verify_stack_slot(inst, src)?;
}
LoadComplex { ref args, .. } => {
self.verify_value_list(inst, args)?;
}
StoreComplex { ref args, .. } => {
self.verify_value_list(inst, args)?;
}
// Exhaustive list so we can't forget to add new formats
Unary { .. } |
@@ -1149,8 +1155,8 @@ impl<'a> Verifier<'a> {
mod tests {
use super::{Error, Verifier};
use entity::EntityList;
use ir::Function;
use ir::instructions::{InstructionData, Opcode};
use ir::Function;
use settings;
macro_rules! assert_err_with_msg {

47
lib/codegen/src/write.rs
View File

@@ -369,12 +369,44 @@ pub fn write_operands(
} => write!(w, " {}, {}{}", arg, stack_slot, offset),
HeapAddr { heap, arg, imm, .. } => write!(w, " {}, {}, {}", heap, arg, imm),
Load { flags, arg, offset, .. } => write!(w, "{} {}{}", flags, arg, offset),
LoadComplex {
flags,
ref args,
offset,
..
} => {
let args = args.as_slice(pool);
write!(
w,
"{} {}{}",
flags,
DisplayValuesWithDelimiter(&args, '+'),
offset
)
}
Store {
flags,
args,
offset,
..
} => write!(w, "{} {}, {}{}", flags, args[0], args[1], offset),
StoreComplex {
flags,
ref args,
offset,
..
} => {
let args = args.as_slice(pool);
write!(
w,
"{} {}, {}{}",
flags,
args[0],
DisplayValuesWithDelimiter(&args[1..], '+'),
offset
)
}
RegMove { arg, src, dst, .. } => {
if let Some(isa) = isa {
let regs = isa.register_info();
@@ -450,6 +482,21 @@ impl<'a> fmt::Display for DisplayValues<'a> {
}
}
struct DisplayValuesWithDelimiter<'a>(&'a [Value], char);
impl<'a> fmt::Display for DisplayValuesWithDelimiter<'a> {
fn fmt(&self, f: &mut fmt::Formatter) -> Result {
for (i, val) in self.0.iter().enumerate() {
if i == 0 {
write!(f, "{}", val)?;
} else {
write!(f, "{}{}", self.1, val)?;
}
}
Ok(())
}
}
#[cfg(test)]
mod tests {
use ir::types;