load_complex and store_complex instructions (#309)
* Start adding the load_complex and store_complex instructions. N.b.: The text format is not correct yet. Requires changes to the lexer and parser. I'm not sure why I needed to change the RuntimeError to Exception yet. Will fix. * Get first few encodings of load_complex working. Still needs var args type checking. * Clean up ModRM helper functions in binemit. * Implement 32-bit displace for load_complex * Use encoding helpers instead of doing them all by hand * Initial implementation of store_complex * Parse value list for load/store_complex with + as delimiter. Looks nice. * Add sign/zero-extension and size variants for load_complex. * Add size variants of store_complex. * Add asm helper lines to load/store complex bin tests. * Example of length-checking the instruction ValueList for an encoding. Extremely questionable implementation. * Fix Python linting issues * First draft of postopt pass to fold adds and loads into load_complex. Just simple loads for now. * Optimization pass now works with all types of loads. * Add store+add -> store_complex to postopt pass * Put complex address optimization behind ISA flag. * Add load/store complex for f32 and f64 * Fixes changes to lexer that broke NaN parsing. Abstracts away the repeated checks for whether or not the characters following a + or - are going to be parsed as a number or not. * Fix formatting issues * Fix register restrictions for complex addresses. * Encoding tests for x86-32. * Add documentation for newly added instructions, recipes, and cdsl changes. * Fix python formatting again * Apply value-list length predicates to all LoadComplex and StoreComplex instructions. * Add predicate types to new encoding helpers for mypy. * Import FieldPredicate to satisfy mypy. * Add and fix some "asm" strings in the encoding tests. * Line-up 'bin' comments in x86/binary64 test * Test parsing of offset-less store_complex instruction. * 'sNaN' not 'sNan' * Bounds check the lookup for polymorphic typevar operand. * Fix encodings for istore16_complex.
This commit is contained in:
Tyler McMullen
committed by
Dan Gohman
Dan Gohman
parent
5aa84a744b
commit
f636d795c5
@@ -3,9 +3,9 @@ x86 Encodings.
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"""
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from __future__ import absolute_import
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from cdsl.predicates import IsUnsignedInt, Not, And
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from base.predicates import IsColocatedFunc, IsColocatedData
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from base.predicates import IsColocatedFunc, IsColocatedData, LengthEquals
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from base import instructions as base
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from base.formats import UnaryImm, FuncAddr, Call
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from base.formats import UnaryImm, FuncAddr, Call, LoadComplex, StoreComplex
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from .defs import X86_64, X86_32
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from . import recipes as r
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from . import settings as cfg
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@@ -19,6 +19,7 @@ try:
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from typing import TYPE_CHECKING, Any # noqa
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if TYPE_CHECKING:
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from cdsl.instructions import MaybeBoundInst # noqa
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from cdsl.predicates import FieldPredicate # noqa
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except ImportError:
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pass
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@@ -54,6 +55,15 @@ def enc_x86_64(inst, recipe, *args, **kwargs):
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X86_64.enc(inst, *recipe(*args, **kwargs))
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def enc_x86_64_instp(inst, recipe, instp, *args, **kwargs):
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# type: (MaybeBoundInst, r.TailRecipe, FieldPredicate, *int, **int) -> None
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"""
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Add encodings for `inst` to X86_64 with and without a REX prefix.
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"""
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X86_64.enc(inst, *recipe.rex(*args, **kwargs), instp=instp)
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X86_64.enc(inst, *recipe(*args, **kwargs), instp=instp)
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def enc_both(inst, recipe, *args, **kwargs):
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# type: (MaybeBoundInst, r.TailRecipe, *int, **Any) -> None
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"""
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@@ -63,6 +73,15 @@ def enc_both(inst, recipe, *args, **kwargs):
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enc_x86_64(inst, recipe, *args, **kwargs)
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def enc_both_instp(inst, recipe, instp, *args, **kwargs):
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# type: (MaybeBoundInst, r.TailRecipe, FieldPredicate, *int, **Any) -> None
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"""
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Add encodings for `inst` to both X86_32 and X86_64.
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"""
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X86_32.enc(inst, *recipe(*args, **kwargs), instp=instp)
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enc_x86_64_instp(inst, recipe, instp, *args, **kwargs)
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def enc_i32_i64(inst, recipe, *args, **kwargs):
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# type: (MaybeBoundInst, r.TailRecipe, *int, **int) -> None
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"""
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@@ -80,6 +99,25 @@ def enc_i32_i64(inst, recipe, *args, **kwargs):
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X86_64.enc(inst.i64, *recipe.rex(*args, w=1, **kwargs))
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def enc_i32_i64_instp(inst, recipe, instp, *args, **kwargs):
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# type: (MaybeBoundInst, r.TailRecipe, FieldPredicate, *int, **int) -> None
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"""
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Add encodings for `inst.i32` to X86_32.
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Add encodings for `inst.i32` to X86_64 with and without REX.
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Add encodings for `inst.i64` to X86_64 with a REX.W prefix.
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Similar to `enc_i32_i64` but applies `instp` to each encoding.
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"""
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X86_32.enc(inst.i32, *recipe(*args, **kwargs), instp=instp)
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# REX-less encoding must come after REX encoding so we don't use it by
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# default. Otherwise reg-alloc would never use r8 and up.
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X86_64.enc(inst.i32, *recipe.rex(*args, **kwargs), instp=instp)
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X86_64.enc(inst.i32, *recipe(*args, **kwargs), instp=instp)
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X86_64.enc(inst.i64, *recipe.rex(*args, w=1, **kwargs), instp=instp)
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def enc_i32_i64_ld_st(inst, w_bit, recipe, *args, **kwargs):
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# type: (MaybeBoundInst, bool, r.TailRecipe, *int, **int) -> None
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"""
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@@ -212,6 +250,31 @@ X86_64.enc(base.ctz.i32, *r.urm(0xf3, 0x0f, 0xbc), isap=cfg.use_bmi1)
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#
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# Loads and stores.
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#
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ldcomplexp = LengthEquals(LoadComplex, 2)
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for recipe in [r.ldWithIndex, r.ldWithIndexDisp8, r.ldWithIndexDisp32]:
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enc_i32_i64_instp(base.load_complex, recipe, ldcomplexp, 0x8b)
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enc_x86_64_instp(base.uload32_complex, recipe, ldcomplexp, 0x8b)
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X86_64.enc(base.sload32_complex, *recipe.rex(0x63, w=1),
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instp=ldcomplexp)
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enc_i32_i64_instp(base.uload16_complex, recipe, ldcomplexp, 0x0f, 0xb7)
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enc_i32_i64_instp(base.sload16_complex, recipe, ldcomplexp, 0x0f, 0xbf)
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enc_i32_i64_instp(base.uload8_complex, recipe, ldcomplexp, 0x0f, 0xb6)
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enc_i32_i64_instp(base.sload8_complex, recipe, ldcomplexp, 0x0f, 0xbe)
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stcomplexp = LengthEquals(StoreComplex, 3)
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for recipe in [r.stWithIndex, r.stWithIndexDisp8, r.stWithIndexDisp32]:
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enc_i32_i64_instp(base.store_complex, recipe, stcomplexp, 0x89)
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enc_x86_64_instp(base.istore32_complex, recipe, stcomplexp, 0x89)
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enc_both_instp(base.istore16_complex.i32, recipe, stcomplexp, 0x66, 0x89)
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enc_x86_64_instp(base.istore16_complex.i64, recipe, stcomplexp, 0x66, 0x89)
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for recipe in [r.stWithIndex_abcd,
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r.stWithIndexDisp8_abcd,
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r.stWithIndexDisp32_abcd]:
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enc_both_instp(base.istore8_complex.i32, recipe, stcomplexp, 0x88)
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enc_x86_64_instp(base.istore8_complex.i64, recipe, stcomplexp, 0x88)
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for recipe in [r.st, r.stDisp8, r.stDisp32]:
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enc_i32_i64_ld_st(base.store, True, recipe, 0x89)
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enc_x86_64(base.istore32.i64.any, recipe, 0x89)
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@@ -286,18 +349,34 @@ enc_both(base.load.f32.any, r.fld, 0xf3, 0x0f, 0x10)
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enc_both(base.load.f32.any, r.fldDisp8, 0xf3, 0x0f, 0x10)
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enc_both(base.load.f32.any, r.fldDisp32, 0xf3, 0x0f, 0x10)
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enc_both(base.load_complex.f32, r.fldWithIndex, 0xf3, 0x0f, 0x10)
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enc_both(base.load_complex.f32, r.fldWithIndexDisp8, 0xf3, 0x0f, 0x10)
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enc_both(base.load_complex.f32, r.fldWithIndexDisp32, 0xf3, 0x0f, 0x10)
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enc_both(base.load.f64.any, r.fld, 0xf2, 0x0f, 0x10)
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enc_both(base.load.f64.any, r.fldDisp8, 0xf2, 0x0f, 0x10)
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enc_both(base.load.f64.any, r.fldDisp32, 0xf2, 0x0f, 0x10)
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enc_both(base.load_complex.f64, r.fldWithIndex, 0xf2, 0x0f, 0x10)
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enc_both(base.load_complex.f64, r.fldWithIndexDisp8, 0xf2, 0x0f, 0x10)
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enc_both(base.load_complex.f64, r.fldWithIndexDisp32, 0xf2, 0x0f, 0x10)
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enc_both(base.store.f32.any, r.fst, 0xf3, 0x0f, 0x11)
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enc_both(base.store.f32.any, r.fstDisp8, 0xf3, 0x0f, 0x11)
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enc_both(base.store.f32.any, r.fstDisp32, 0xf3, 0x0f, 0x11)
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enc_both(base.store_complex.f32, r.fstWithIndex, 0xf3, 0x0f, 0x11)
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enc_both(base.store_complex.f32, r.fstWithIndexDisp8, 0xf3, 0x0f, 0x11)
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enc_both(base.store_complex.f32, r.fstWithIndexDisp32, 0xf3, 0x0f, 0x11)
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enc_both(base.store.f64.any, r.fst, 0xf2, 0x0f, 0x11)
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enc_both(base.store.f64.any, r.fstDisp8, 0xf2, 0x0f, 0x11)
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enc_both(base.store.f64.any, r.fstDisp32, 0xf2, 0x0f, 0x11)
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enc_both(base.store_complex.f64, r.fstWithIndex, 0xf2, 0x0f, 0x11)
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enc_both(base.store_complex.f64, r.fstWithIndexDisp8, 0xf2, 0x0f, 0x11)
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enc_both(base.store_complex.f64, r.fstWithIndexDisp32, 0xf2, 0x0f, 0x11)
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enc_both(base.fill.f32, r.ffillSib32, 0xf3, 0x0f, 0x10)
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enc_both(base.regfill.f32, r.fregfill32, 0xf3, 0x0f, 0x10)
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enc_both(base.fill.f64, r.ffillSib32, 0xf2, 0x0f, 0x10)
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@@ -14,6 +14,7 @@ from base.formats import IntSelect, IntCondTrap, FloatCondTrap
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from base.formats import Jump, Branch, BranchInt, BranchFloat
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from base.formats import Ternary, FuncAddr, UnaryGlobalVar
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from base.formats import RegMove, RegSpill, RegFill, CopySpecial
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from base.formats import LoadComplex, StoreComplex
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from .registers import GPR, ABCD, FPR, GPR_DEREF_SAFE, GPR_ZERO_DEREF_SAFE
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from .registers import GPR8, FPR8, GPR8_DEREF_SAFE, GPR8_ZERO_DEREF_SAFE, FLAG
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from .registers import StackGPR32, StackFPR32
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@@ -739,6 +740,22 @@ st = TailRecipe(
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modrm_rm(in_reg1, in_reg0, sink);
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''')
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# XX /r register-indirect store with index and no offset.
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stWithIndex = TailRecipe(
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'stWithIndex', StoreComplex, size=2,
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ins=(GPR, GPR_ZERO_DEREF_SAFE, GPR_DEREF_SAFE),
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outs=(),
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instp=IsEqual(StoreComplex.offset, 0),
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clobbers_flags=False,
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emit='''
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if !flags.notrap() {
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sink.trap(TrapCode::HeapOutOfBounds, func.srclocs[inst]);
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}
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PUT_OP(bits, rex3(in_reg1, in_reg0, in_reg2), sink);
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modrm_sib(in_reg0, sink);
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sib(0, in_reg2, in_reg1, sink);
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''')
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# XX /r register-indirect store with no offset.
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# Only ABCD allowed for stored value. This is for byte stores with no REX.
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st_abcd = TailRecipe(
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@@ -754,6 +771,23 @@ st_abcd = TailRecipe(
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modrm_rm(in_reg1, in_reg0, sink);
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''')
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# XX /r register-indirect store with index and no offset.
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# Only ABCD allowed for stored value. This is for byte stores with no REX.
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stWithIndex_abcd = TailRecipe(
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'stWithIndex_abcd', StoreComplex, size=2,
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ins=(ABCD, GPR_ZERO_DEREF_SAFE, GPR_DEREF_SAFE),
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outs=(),
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instp=IsEqual(StoreComplex.offset, 0),
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clobbers_flags=False,
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emit='''
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if !flags.notrap() {
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sink.trap(TrapCode::HeapOutOfBounds, func.srclocs[inst]);
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}
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PUT_OP(bits, rex3(in_reg1, in_reg0, in_reg2), sink);
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modrm_sib(in_reg0, sink);
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sib(0, in_reg2, in_reg1, sink);
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''')
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# XX /r register-indirect store of FPR with no offset.
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fst = TailRecipe(
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'fst', Store, size=1, ins=(FPR, GPR_ZERO_DEREF_SAFE), outs=(),
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@@ -766,6 +800,20 @@ fst = TailRecipe(
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PUT_OP(bits, rex2(in_reg1, in_reg0), sink);
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modrm_rm(in_reg1, in_reg0, sink);
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''')
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# XX /r register-indirect store with index and no offset of FPR.
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fstWithIndex = TailRecipe(
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'fstWithIndex', StoreComplex, size=2,
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ins=(FPR, GPR_ZERO_DEREF_SAFE, GPR_DEREF_SAFE), outs=(),
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instp=IsEqual(StoreComplex.offset, 0),
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clobbers_flags=False,
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emit='''
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if !flags.notrap() {
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sink.trap(TrapCode::HeapOutOfBounds, func.srclocs[inst]);
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}
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PUT_OP(bits, rex3(in_reg1, in_reg0, in_reg2), sink);
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modrm_sib(in_reg0, sink);
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sib(0, in_reg2, in_reg1, sink);
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''')
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# XX /r register-indirect store with 8-bit offset.
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stDisp8 = TailRecipe(
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@@ -781,6 +829,27 @@ stDisp8 = TailRecipe(
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let offset: i32 = offset.into();
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sink.put1(offset as u8);
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''')
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# XX /r register-indirect store with index and 8-bit offset.
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stWithIndexDisp8 = TailRecipe(
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'stWithIndexDisp8', StoreComplex, size=3,
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ins=(GPR, GPR, GPR_DEREF_SAFE),
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outs=(),
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instp=IsSignedInt(StoreComplex.offset, 8),
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clobbers_flags=False,
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emit='''
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if !flags.notrap() {
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sink.trap(TrapCode::HeapOutOfBounds, func.srclocs[inst]);
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}
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PUT_OP(bits, rex3(in_reg1, in_reg0, in_reg2), sink);
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modrm_sib_disp8(in_reg0, sink);
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sib(0, in_reg2, in_reg1, sink);
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let offset: i32 = offset.into();
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sink.put1(offset as u8);
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''')
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# XX /r register-indirect store with 8-bit offset.
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# Only ABCD allowed for stored value. This is for byte stores with no REX.
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stDisp8_abcd = TailRecipe(
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'stDisp8_abcd', Store, size=2, ins=(ABCD, GPR), outs=(),
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instp=IsSignedInt(Store.offset, 8),
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@@ -795,6 +864,27 @@ stDisp8_abcd = TailRecipe(
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let offset: i32 = offset.into();
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sink.put1(offset as u8);
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''')
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# XX /r register-indirect store with index and 8-bit offset.
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# Only ABCD allowed for stored value. This is for byte stores with no REX.
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stWithIndexDisp8_abcd = TailRecipe(
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'stWithIndexDisp8_abcd', StoreComplex, size=3,
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ins=(ABCD, GPR, GPR_DEREF_SAFE),
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outs=(),
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instp=IsSignedInt(StoreComplex.offset, 8),
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clobbers_flags=False,
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emit='''
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if !flags.notrap() {
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sink.trap(TrapCode::HeapOutOfBounds, func.srclocs[inst]);
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}
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PUT_OP(bits, rex3(in_reg1, in_reg0, in_reg2), sink);
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modrm_sib_disp8(in_reg0, sink);
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sib(0, in_reg2, in_reg1, sink);
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let offset: i32 = offset.into();
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sink.put1(offset as u8);
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''')
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# XX /r register-indirect store with 8-bit offset of FPR.
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fstDisp8 = TailRecipe(
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'fstDisp8', Store, size=2, ins=(FPR, GPR_DEREF_SAFE), outs=(),
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instp=IsSignedInt(Store.offset, 8),
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@@ -809,6 +899,24 @@ fstDisp8 = TailRecipe(
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sink.put1(offset as u8);
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''')
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# XX /r register-indirect store with index and 8-bit offset of FPR.
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fstWithIndexDisp8 = TailRecipe(
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'fstWithIndexDisp8', StoreComplex, size=3,
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ins=(FPR, GPR, GPR_DEREF_SAFE),
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outs=(),
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instp=IsSignedInt(StoreComplex.offset, 8),
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clobbers_flags=False,
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emit='''
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if !flags.notrap() {
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sink.trap(TrapCode::HeapOutOfBounds, func.srclocs[inst]);
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}
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PUT_OP(bits, rex3(in_reg1, in_reg0, in_reg2), sink);
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modrm_sib_disp8(in_reg0, sink);
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sib(0, in_reg2, in_reg1, sink);
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let offset: i32 = offset.into();
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sink.put1(offset as u8);
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''')
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# XX /r register-indirect store with 32-bit offset.
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stDisp32 = TailRecipe(
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'stDisp32', Store, size=5, ins=(GPR, GPR_DEREF_SAFE), outs=(),
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@@ -822,6 +930,27 @@ stDisp32 = TailRecipe(
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let offset: i32 = offset.into();
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sink.put4(offset as u32);
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''')
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# XX /r register-indirect store with index and 32-bit offset.
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stWithIndexDisp32 = TailRecipe(
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'stWithIndexDisp32', StoreComplex, size=6,
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ins=(GPR, GPR, GPR_DEREF_SAFE),
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outs=(),
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instp=IsSignedInt(StoreComplex.offset, 32),
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clobbers_flags=False,
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emit='''
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if !flags.notrap() {
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sink.trap(TrapCode::HeapOutOfBounds, func.srclocs[inst]);
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}
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PUT_OP(bits, rex3(in_reg1, in_reg0, in_reg2), sink);
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modrm_sib_disp32(in_reg0, sink);
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sib(0, in_reg2, in_reg1, sink);
|
||||
let offset: i32 = offset.into();
|
||||
sink.put4(offset as u32);
|
||||
''')
|
||||
|
||||
# XX /r register-indirect store with 32-bit offset.
|
||||
# Only ABCD allowed for stored value. This is for byte stores with no REX.
|
||||
stDisp32_abcd = TailRecipe(
|
||||
'stDisp32_abcd', Store, size=5, ins=(ABCD, GPR), outs=(),
|
||||
when_prefixed=stDisp32,
|
||||
@@ -835,6 +964,27 @@ stDisp32_abcd = TailRecipe(
|
||||
let offset: i32 = offset.into();
|
||||
sink.put4(offset as u32);
|
||||
''')
|
||||
|
||||
# XX /r register-indirect store with index and 32-bit offset.
|
||||
# Only ABCD allowed for stored value. This is for byte stores with no REX.
|
||||
stWithIndexDisp32_abcd = TailRecipe(
|
||||
'stWithIndexDisp32_abcd', StoreComplex, size=6,
|
||||
ins=(ABCD, GPR, GPR_DEREF_SAFE),
|
||||
outs=(),
|
||||
instp=IsSignedInt(StoreComplex.offset, 32),
|
||||
clobbers_flags=False,
|
||||
emit='''
|
||||
if !flags.notrap() {
|
||||
sink.trap(TrapCode::HeapOutOfBounds, func.srclocs[inst]);
|
||||
}
|
||||
PUT_OP(bits, rex3(in_reg1, in_reg0, in_reg2), sink);
|
||||
modrm_sib_disp32(in_reg0, sink);
|
||||
sib(0, in_reg2, in_reg1, sink);
|
||||
let offset: i32 = offset.into();
|
||||
sink.put4(offset as u32);
|
||||
''')
|
||||
|
||||
# XX /r register-indirect store with 32-bit offset of FPR.
|
||||
fstDisp32 = TailRecipe(
|
||||
'fstDisp32', Store, size=5, ins=(FPR, GPR_DEREF_SAFE), outs=(),
|
||||
clobbers_flags=False,
|
||||
@@ -848,6 +998,24 @@ fstDisp32 = TailRecipe(
|
||||
sink.put4(offset as u32);
|
||||
''')
|
||||
|
||||
# XX /r register-indirect store with index and 32-bit offset of FPR.
|
||||
fstWithIndexDisp32 = TailRecipe(
|
||||
'fstWithIndexDisp32', StoreComplex, size=6,
|
||||
ins=(FPR, GPR, GPR_DEREF_SAFE),
|
||||
outs=(),
|
||||
instp=IsSignedInt(StoreComplex.offset, 32),
|
||||
clobbers_flags=False,
|
||||
emit='''
|
||||
if !flags.notrap() {
|
||||
sink.trap(TrapCode::HeapOutOfBounds, func.srclocs[inst]);
|
||||
}
|
||||
PUT_OP(bits, rex3(in_reg1, in_reg0, in_reg2), sink);
|
||||
modrm_sib_disp32(in_reg0, sink);
|
||||
sib(0, in_reg2, in_reg1, sink);
|
||||
let offset: i32 = offset.into();
|
||||
sink.put4(offset as u32);
|
||||
''')
|
||||
|
||||
# Unary spill with SIB and 32-bit displacement.
|
||||
spillSib32 = TailRecipe(
|
||||
'spillSib32', Unary, size=6, ins=GPR, outs=StackGPR32,
|
||||
@@ -919,6 +1087,22 @@ ld = TailRecipe(
|
||||
modrm_rm(in_reg0, out_reg0, sink);
|
||||
''')
|
||||
|
||||
# XX /r load with index and no offset.
|
||||
ldWithIndex = TailRecipe(
|
||||
'ldWithIndex', LoadComplex, size=2,
|
||||
ins=(GPR_ZERO_DEREF_SAFE, GPR_DEREF_SAFE),
|
||||
outs=(GPR),
|
||||
instp=IsEqual(LoadComplex.offset, 0),
|
||||
clobbers_flags=False,
|
||||
emit='''
|
||||
if !flags.notrap() {
|
||||
sink.trap(TrapCode::HeapOutOfBounds, func.srclocs[inst]);
|
||||
}
|
||||
PUT_OP(bits, rex3(in_reg0, out_reg0, in_reg1), sink);
|
||||
modrm_sib(out_reg0, sink);
|
||||
sib(0, in_reg1, in_reg0, sink);
|
||||
''')
|
||||
|
||||
# XX /r float load with no offset.
|
||||
fld = TailRecipe(
|
||||
'fld', Load, size=1, ins=(GPR_ZERO_DEREF_SAFE), outs=(FPR),
|
||||
@@ -932,6 +1116,22 @@ fld = TailRecipe(
|
||||
modrm_rm(in_reg0, out_reg0, sink);
|
||||
''')
|
||||
|
||||
# XX /r float load with index and no offset.
|
||||
fldWithIndex = TailRecipe(
|
||||
'fldWithIndex', LoadComplex, size=2,
|
||||
ins=(GPR_ZERO_DEREF_SAFE, GPR_DEREF_SAFE),
|
||||
outs=(FPR),
|
||||
instp=IsEqual(LoadComplex.offset, 0),
|
||||
clobbers_flags=False,
|
||||
emit='''
|
||||
if !flags.notrap() {
|
||||
sink.trap(TrapCode::HeapOutOfBounds, func.srclocs[inst]);
|
||||
}
|
||||
PUT_OP(bits, rex3(in_reg0, out_reg0, in_reg1), sink);
|
||||
modrm_sib(out_reg0, sink);
|
||||
sib(0, in_reg1, in_reg0, sink);
|
||||
''')
|
||||
|
||||
# XX /r load with 8-bit offset.
|
||||
ldDisp8 = TailRecipe(
|
||||
'ldDisp8', Load, size=2, ins=(GPR_DEREF_SAFE), outs=(GPR),
|
||||
@@ -947,6 +1147,24 @@ ldDisp8 = TailRecipe(
|
||||
sink.put1(offset as u8);
|
||||
''')
|
||||
|
||||
# XX /r load with index and 8-bit offset.
|
||||
ldWithIndexDisp8 = TailRecipe(
|
||||
'ldWithIndexDisp8', LoadComplex, size=3,
|
||||
ins=(GPR, GPR_DEREF_SAFE),
|
||||
outs=(GPR),
|
||||
instp=IsSignedInt(LoadComplex.offset, 8),
|
||||
clobbers_flags=False,
|
||||
emit='''
|
||||
if !flags.notrap() {
|
||||
sink.trap(TrapCode::HeapOutOfBounds, func.srclocs[inst]);
|
||||
}
|
||||
PUT_OP(bits, rex3(in_reg0, out_reg0, in_reg1), sink);
|
||||
modrm_sib_disp8(out_reg0, sink);
|
||||
sib(0, in_reg1, in_reg0, sink);
|
||||
let offset: i32 = offset.into();
|
||||
sink.put1(offset as u8);
|
||||
''')
|
||||
|
||||
# XX /r float load with 8-bit offset.
|
||||
fldDisp8 = TailRecipe(
|
||||
'fldDisp8', Load, size=2, ins=(GPR_DEREF_SAFE), outs=(FPR),
|
||||
@@ -962,6 +1180,24 @@ fldDisp8 = TailRecipe(
|
||||
sink.put1(offset as u8);
|
||||
''')
|
||||
|
||||
# XX /r float load with 8-bit offset.
|
||||
fldWithIndexDisp8 = TailRecipe(
|
||||
'fldWithIndexDisp8', LoadComplex, size=3,
|
||||
ins=(GPR, GPR_DEREF_SAFE),
|
||||
outs=(FPR),
|
||||
instp=IsSignedInt(LoadComplex.offset, 8),
|
||||
clobbers_flags=False,
|
||||
emit='''
|
||||
if !flags.notrap() {
|
||||
sink.trap(TrapCode::HeapOutOfBounds, func.srclocs[inst]);
|
||||
}
|
||||
PUT_OP(bits, rex3(in_reg0, out_reg0, in_reg1), sink);
|
||||
modrm_sib_disp8(out_reg0, sink);
|
||||
sib(0, in_reg1, in_reg0, sink);
|
||||
let offset: i32 = offset.into();
|
||||
sink.put1(offset as u8);
|
||||
''')
|
||||
|
||||
# XX /r load with 32-bit offset.
|
||||
ldDisp32 = TailRecipe(
|
||||
'ldDisp32', Load, size=5, ins=(GPR_DEREF_SAFE), outs=(GPR),
|
||||
@@ -977,6 +1213,24 @@ ldDisp32 = TailRecipe(
|
||||
sink.put4(offset as u32);
|
||||
''')
|
||||
|
||||
# XX /r load with index and 32-bit offset.
|
||||
ldWithIndexDisp32 = TailRecipe(
|
||||
'ldWithIndexDisp32', LoadComplex, size=6,
|
||||
ins=(GPR, GPR_DEREF_SAFE),
|
||||
outs=(GPR),
|
||||
instp=IsSignedInt(LoadComplex.offset, 32),
|
||||
clobbers_flags=False,
|
||||
emit='''
|
||||
if !flags.notrap() {
|
||||
sink.trap(TrapCode::HeapOutOfBounds, func.srclocs[inst]);
|
||||
}
|
||||
PUT_OP(bits, rex3(in_reg0, out_reg0, in_reg1), sink);
|
||||
modrm_sib_disp32(out_reg0, sink);
|
||||
sib(0, in_reg1, in_reg0, sink);
|
||||
let offset: i32 = offset.into();
|
||||
sink.put4(offset as u32);
|
||||
''')
|
||||
|
||||
# XX /r float load with 32-bit offset.
|
||||
fldDisp32 = TailRecipe(
|
||||
'fldDisp32', Load, size=5, ins=(GPR_DEREF_SAFE), outs=(FPR),
|
||||
@@ -992,6 +1246,24 @@ fldDisp32 = TailRecipe(
|
||||
sink.put4(offset as u32);
|
||||
''')
|
||||
|
||||
# XX /r float load with index and 32-bit offset.
|
||||
fldWithIndexDisp32 = TailRecipe(
|
||||
'fldWithIndexDisp32', LoadComplex, size=6,
|
||||
ins=(GPR, GPR_DEREF_SAFE),
|
||||
outs=(FPR),
|
||||
instp=IsSignedInt(LoadComplex.offset, 32),
|
||||
clobbers_flags=False,
|
||||
emit='''
|
||||
if !flags.notrap() {
|
||||
sink.trap(TrapCode::HeapOutOfBounds, func.srclocs[inst]);
|
||||
}
|
||||
PUT_OP(bits, rex3(in_reg0, out_reg0, in_reg1), sink);
|
||||
modrm_sib_disp32(out_reg0, sink);
|
||||
sib(0, in_reg1, in_reg0, sink);
|
||||
let offset: i32 = offset.into();
|
||||
sink.put4(offset as u32);
|
||||
''')
|
||||
|
||||
# Unary fill with SIB and 32-bit displacement.
|
||||
fillSib32 = TailRecipe(
|
||||
'fillSib32', Unary, size=6, ins=StackGPR32, outs=GPR,
|
||||
|
||||
Reference in New Issue
Block a user