load_complex and store_complex instructions (#309)
* Start adding the load_complex and store_complex instructions. N.b.: The text format is not correct yet. Requires changes to the lexer and parser. I'm not sure why I needed to change the RuntimeError to Exception yet. Will fix. * Get first few encodings of load_complex working. Still needs var args type checking. * Clean up ModRM helper functions in binemit. * Implement 32-bit displace for load_complex * Use encoding helpers instead of doing them all by hand * Initial implementation of store_complex * Parse value list for load/store_complex with + as delimiter. Looks nice. * Add sign/zero-extension and size variants for load_complex. * Add size variants of store_complex. * Add asm helper lines to load/store complex bin tests. * Example of length-checking the instruction ValueList for an encoding. Extremely questionable implementation. * Fix Python linting issues * First draft of postopt pass to fold adds and loads into load_complex. Just simple loads for now. * Optimization pass now works with all types of loads. * Add store+add -> store_complex to postopt pass * Put complex address optimization behind ISA flag. * Add load/store complex for f32 and f64 * Fixes changes to lexer that broke NaN parsing. Abstracts away the repeated checks for whether or not the characters following a + or - are going to be parsed as a number or not. * Fix formatting issues * Fix register restrictions for complex addresses. * Encoding tests for x86-32. * Add documentation for newly added instructions, recipes, and cdsl changes. * Fix python formatting again * Apply value-list length predicates to all LoadComplex and StoreComplex instructions. * Add predicate types to new encoding helpers for mypy. * Import FieldPredicate to satisfy mypy. * Add and fix some "asm" strings in the encoding tests. * Line-up 'bin' comments in x86/binary64 test * Test parsing of offset-less store_complex instruction. * 'sNaN' not 'sNan' * Bounds check the lookup for polymorphic typevar operand. * Fix encodings for istore16_complex.
This commit is contained in:
Tyler McMullen
committed by
Dan Gohman
Dan Gohman
parent
5aa84a744b
commit
f636d795c5
@@ -476,6 +476,11 @@ these instructions is undefined. If it is addressable but not
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There are also more restricted operations for accessing specific types of memory
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objects.
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Additionally, instructions are provided for handling multi-register addressing.
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.. autoinst:: load_complex
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.. autoinst:: store_complex
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Memory operation flags
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----------------------
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@@ -227,6 +227,32 @@ ebb0:
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; asm: ucomiss %xmm5, %xmm5
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[-,%rflags] v312 = ffcmp v10, v10 ; bin: 0f 2e ed
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; Load/Store Complex
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[-,%rax] v350 = iconst.i32 1
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[-,%rbx] v351 = iconst.i32 2
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; asm: movss (%rax,%rbx,1),%xmm5
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[-,%xmm5] v352 = load_complex.f32 v350+v351 ; bin: heap_oob f3 0f 10 2c 18
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; asm: movss 0x32(%rax,%rbx,1),%xmm5
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[-,%xmm5] v353 = load_complex.f32 v350+v351+50 ; bin: heap_oob f3 0f 10 6c 18 32
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; asm: movss -0x32(%rax,%rbx,1),%xmm5
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[-,%xmm5] v354 = load_complex.f32 v350+v351-50 ; bin: heap_oob f3 0f 10 6c 18 ce
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; asm: movss 0x2710(%rax,%rbx,1),%xmm5
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[-,%xmm5] v355 = load_complex.f32 v350+v351+10000 ; bin: heap_oob f3 0f 10 ac 18 00002710
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; asm: movss -0x2710(%rax,%rbx,1),%xmm5
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[-,%xmm5] v356 = load_complex.f32 v350+v351-10000 ; bin: heap_oob f3 0f 10 ac 18 ffffd8f0
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; asm: movss %xmm5,(%rax,%rbx,1)
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[-] store_complex.f32 v100, v350+v351 ; bin: heap_oob f3 0f 11 2c 18
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; asm: movss %xmm5,0x32(%rax,%rbx,1)
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[-] store_complex.f32 v100, v350+v351+50 ; bin: heap_oob f3 0f 11 6c 18 32
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; asm: movss %xmm2,-0x32(%rax,%rbx,1)
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[-] store_complex.f32 v101, v350+v351-50 ; bin: heap_oob f3 0f 11 54 18 ce
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; asm: movss %xmm5,0x2710(%rax,%rbx,1)
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[-] store_complex.f32 v100, v350+v351+10000 ; bin: heap_oob f3 0f 11 ac 18 00002710
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; asm: movss %xmm2,-0x2710(%rax,%rbx,1)
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[-] store_complex.f32 v101, v350+v351-10000 ; bin: heap_oob f3 0f 11 94 18 ffffd8f0
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return
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}
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@@ -432,6 +432,37 @@ ebb0:
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; asm: shrl $8, %esi
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[-,%rsi] v515 = ushr_imm v2, 8 ; bin: c1 ee 08
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; Load Complex
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[-,%rax] v521 = iconst.i32 1
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[-,%rbx] v522 = iconst.i32 1
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; asm: movl (%eax,%ebx,1), %ecx
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[-,%rcx] v526 = load_complex.i32 v521+v522 ; bin: heap_oob 8b 0c 18
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; asm: movl 1(%eax,%ebx,1), %ecx
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[-,%rcx] v528 = load_complex.i32 v521+v522+1 ; bin: heap_oob 8b 4c 18 01
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; asm: mov 0x100000(%eax,%ebx,1),%ecx
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[-,%rcx] v530 = load_complex.i32 v521+v522+0x1000 ; bin: heap_oob 8b 8c 18 00001000
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; asm: movzbl (%eax,%ebx,1),%ecx
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[-,%rcx] v532 = uload8_complex.i32 v521+v522 ; bin: heap_oob 0f b6 0c 18
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; asm: movsbl (%eax,%ebx,1),%ecx
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[-,%rcx] v534 = sload8_complex.i32 v521+v522 ; bin: heap_oob 0f be 0c 18
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; asm: movzwl (%eax,%ebx,1),%ecx
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[-,%rcx] v536 = uload16_complex.i32 v521+v522 ; bin: heap_oob 0f b7 0c 18
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; asm: movswl (%eax,%ebx,1),%ecx
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[-,%rcx] v538 = sload16_complex.i32 v521+v522 ; bin: heap_oob 0f bf 0c 18
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; Store Complex
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[-,%rcx] v601 = iconst.i32 1
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; asm: mov %ecx,(%eax,%ebx,1)
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store_complex v601, v521+v522 ; bin: heap_oob 89 0c 18
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; asm: mov %ecx,0x1(%eax,%ebx,1)
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store_complex v601, v521+v522+1 ; bin: heap_oob 89 4c 18 01
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; asm: mov %ecx,0x100000(%eax,%ebx,1)
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store_complex v601, v521+v522+0x1000 ; bin: heap_oob 89 8c 18 00001000
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; asm: mov %cx,(%eax,%ebx,1)
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istore16_complex v601, v521+v522 ; bin: heap_oob 66 89 0c 18
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; asm: mov %cl,(%eax,%ebx,1)
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istore8_complex v601, v521+v522 ; bin: heap_oob 88 0c 18
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; asm: testl %ecx, %ecx
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; asm: je ebb1
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brz v1, ebb1 ; bin: 85 c9 74 0e
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@@ -241,6 +241,34 @@ ebb0:
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; asm: ucomiss %xmm5, %xmm5
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[-,%rflags] v312 = ffcmp v10, v10 ; bin: 0f 2e ed
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; Load/Store Complex
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[-,%rax] v350 = iconst.i64 1
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[-,%rbx] v351 = iconst.i64 2
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; asm: movss (%rax,%rbx,1),%xmm5
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[-,%xmm5] v352 = load_complex.f32 v350+v351 ; bin: heap_oob f3 0f 10 2c 18
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; asm: movss 0x32(%rax,%rbx,1),%xmm5
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[-,%xmm5] v353 = load_complex.f32 v350+v351+50 ; bin: heap_oob f3 0f 10 6c 18 32
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; asm: movss -0x32(%rax,%rbx,1),%xmm10
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[-,%xmm10] v354 = load_complex.f32 v350+v351-50 ; bin: heap_oob f3 44 0f 10 54 18 ce
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; asm: 0x2710(%rax,%rbx,1),%xmm5
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[-,%xmm5] v355 = load_complex.f32 v350+v351+10000 ; bin: heap_oob f3 0f 10 ac 18 00002710
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; asm: -0x2710(%rax,%rbx,1),%xmm10
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[-,%xmm10] v356 = load_complex.f32 v350+v351-10000 ; bin: heap_oob f3 44 0f 10 94 18 ffffd8f0
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; asm: movsd %xmm5, (%rax,%rbx,1)
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[-] store_complex.f32 v100, v350+v351 ; bin: heap_oob f3 0f 11 2c 18
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; asm: movsd %xmm5, 50(%rax,%rbx,1)
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[-] store_complex.f32 v100, v350+v351+50 ; bin: heap_oob f3 0f 11 6c 18 32
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; asm: movsd %xmm10, -50(%rax,%rbx,1)
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[-] store_complex.f32 v101, v350+v351-50 ; bin: heap_oob f3 44 0f 11 54 18 ce
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; asm: movsd %xmm5, 10000(%rax,%rbx,1)
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[-] store_complex.f32 v100, v350+v351+10000 ; bin: heap_oob f3 0f 11 ac 18 00002710
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; asm: movsd %xmm10, -10000(%rax,%rbx,1)
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[-] store_complex.f32 v101, v350+v351-10000 ; bin: heap_oob f3 44 0f 11 94 18 ffffd8f0
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return
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}
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@@ -476,6 +504,32 @@ ebb0:
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; asm: ucomisd %xmm5, %xmm5
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[-,%rflags] v312 = ffcmp v10, v10 ; bin: 66 0f 2e ed
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; Load/Store Complex
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[-,%rax] v350 = iconst.i64 1
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[-,%rbx] v351 = iconst.i64 2
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; asm: movsd (%rax,%rbx,1),%xmm5
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[-,%xmm5] v352 = load_complex.f64 v350+v351 ; bin: heap_oob f2 0f 10 2c 18
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; asm: movsd 0x32(%rax,%rbx,1),%xmm5
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[-,%xmm5] v353 = load_complex.f64 v350+v351+50 ; bin: heap_oob f2 0f 10 6c 18 32
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; asm: movsd -0x32(%rax,%rbx,1),%xmm10
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[-,%xmm10] v354 = load_complex.f64 v350+v351-50 ; bin: heap_oob f2 44 0f 10 54 18 ce
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; asm: movsd 0x2710(%rax,%rbx,1),%xmm5
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[-,%xmm5] v355 = load_complex.f64 v350+v351+10000 ; bin: heap_oob f2 0f 10 ac 18 00002710
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; asm: movsd -0x2710(%rax,%rbx,1),%xmm10
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[-,%xmm10] v356 = load_complex.f64 v350+v351-10000 ; bin: heap_oob f2 44 0f 10 94 18 ffffd8f0
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; asm: movsd %xmm5, (%rax,%rbx,1)
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[-] store_complex.f64 v100, v350+v351 ; bin: heap_oob f2 0f 11 2c 18
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; asm: movsd %xmm5, 50(%rax,%rbx,1)
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[-] store_complex.f64 v100, v350+v351+50 ; bin: heap_oob f2 0f 11 6c 18 32
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; asm: movsd %xmm10, -50(%rax,%rbx,1)
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[-] store_complex.f64 v101, v350+v351-50 ; bin: heap_oob f2 44 0f 11 54 18 ce
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; asm: movsd %xmm5, 10000(%rax,%rbx,1)
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[-] store_complex.f64 v100, v350+v351+10000 ; bin: heap_oob f2 0f 11 ac 18 00002710
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; asm: movsd %xmm10, -10000(%rax,%rbx,1)
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[-] store_complex.f64 v101, v350+v351-10000 ; bin: heap_oob f2 44 0f 11 94 18 ffffd8f0
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return
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}
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@@ -594,6 +594,80 @@ ebb0:
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[-,%r8] v520 = ushr_imm v4, 63 ; bin: 49 c1 e8 3f
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; Load Complex
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[-,%rax] v521 = iconst.i64 1
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[-,%rbx] v522 = iconst.i64 1
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[-,%rdi] v523 = iconst.i32 1
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[-,%rsi] v524 = iconst.i32 1
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; asm: movq (%rax,%rbx,1), %rcx
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[-,%rcx] v525 = load_complex.i64 v521+v522 ; bin: heap_oob 48 8b 0c 18
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; asm: movl (%rax,%rbx,1), %ecx
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[-,%rcx] v526 = load_complex.i32 v521+v522 ; bin: heap_oob 8b 0c 18
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; asm: movq 1(%rax,%rbx,1), %rcx
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[-,%rcx] v527 = load_complex.i64 v521+v522+1 ; bin: heap_oob 48 8b 4c 18 01
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; asm: movl 1(%rax,%rbx,1), %ecx
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[-,%rcx] v528 = load_complex.i32 v521+v522+1 ; bin: heap_oob 8b 4c 18 01
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; asm: mov 0x100000(%rax,%rbx,1),%rcx
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[-,%rcx] v529 = load_complex.i64 v521+v522+0x1000 ; bin: heap_oob 48 8b 8c 18 00001000
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; asm: mov 0x100000(%rax,%rbx,1),%ecx
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[-,%rcx] v530 = load_complex.i32 v521+v522+0x1000 ; bin: heap_oob 8b 8c 18 00001000
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; asm: movzbq (%rax,%rbx,1),%rcx
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[-,%rcx] v531 = uload8_complex.i64 v521+v522 ; bin: heap_oob 48 0f b6 0c 18
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; asm: movzbl (%rax,%rbx,1),%ecx
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[-,%rcx] v532 = uload8_complex.i32 v521+v522 ; bin: heap_oob 0f b6 0c 18
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; asm: movsbq (%rax,%rbx,1),%rcx
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[-,%rcx] v533 = sload8_complex.i64 v521+v522 ; bin: heap_oob 48 0f be 0c 18
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; asm: movsbl (%rax,%rbx,1),%ecx
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[-,%rcx] v534 = sload8_complex.i32 v521+v522 ; bin: heap_oob 0f be 0c 18
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; asm: movzwq (%rax,%rbx,1),%rcx
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[-,%rcx] v535 = uload16_complex.i64 v521+v522 ; bin: heap_oob 48 0f b7 0c 18
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; asm: movzwl (%rax,%rbx,1),%ecx
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[-,%rcx] v536 = uload16_complex.i32 v521+v522 ; bin: heap_oob 0f b7 0c 18
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; asm: movswq (%rax,%rbx,1),%rcx
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[-,%rcx] v537 = sload16_complex.i64 v521+v522 ; bin: heap_oob 48 0f bf 0c 18
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; asm: movswl (%rax,%rbx,1),%ecx
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[-,%rcx] v538 = sload16_complex.i32 v521+v522 ; bin: heap_oob 0f bf 0c 18
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; asm: mov (%rax,%rbx,1),%ecx
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[-,%rcx] v539 = uload32_complex v521+v522 ; bin: heap_oob 8b 0c 18
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; asm: movslq (%rax,%rbx,1),%rcx
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[-,%rcx] v540 = sload32_complex v521+v522 ; bin: heap_oob 48 63 0c 18
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[-,%r13] v550 = iconst.i64 1
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[-,%r14] v551 = iconst.i64 1
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; asm: mov 0x0(%r13,%r14,1),%r12d
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[-,%r12] v552 = load_complex.i32 v550+v551 ; bin: heap_oob 47 8b 64 35 00
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; Store Complex
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[-,%rcx] v600 = iconst.i64 1
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[-,%rcx] v601 = iconst.i32 1
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[-,%r10] v602 = iconst.i64 1
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[-,%r11] v603 = iconst.i32 1
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; asm: mov %rcx,(%rax,%rbx,1)
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store_complex v600, v521+v522 ; bin: heap_oob 48 89 0c 18
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; asm: mov %rcx,0x1(%rax,%rbx,1)
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store_complex v600, v521+v522+1 ; bin: heap_oob 48 89 4c 18 01
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; asm: mov %rcx,0x100000(%rax,%rbx,1)
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store_complex v600, v521+v522+0x1000 ; bin: heap_oob 48 89 8c 18 00001000
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; asm: mov %ecx,(%rax,%rbx,1)
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store_complex v601, v521+v522 ; bin: heap_oob 89 0c 18
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; asm: mov %ecx,0x1(%rax,%rbx,1)
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store_complex v601, v521+v522+1 ; bin: heap_oob 89 4c 18 01
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; asm: mov %ecx,0x100000(%rax,%rbx,1)
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store_complex v601, v521+v522+0x1000 ; bin: heap_oob 89 8c 18 00001000
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; asm: mov %ecx,(%rax,%rbx,1)
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istore32_complex v600, v521+v522 ; bin: heap_oob 89 0c 18
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; asm: mov %cx,(%rax,%rbx,1)
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istore16_complex v600, v521+v522 ; bin: heap_oob 66 89 0c 18
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; asm: mov %cx,(%rax,%rbx,1)
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istore16_complex v601, v521+v522 ; bin: heap_oob 66 89 0c 18
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; asm: mov %r10w,(%rax,%rbx,1)
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istore16_complex v602, v521+v522 ; bin: heap_oob 66 44 89 14 18
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; asm: mov %r11w,(%rax,%rbx,1)
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istore16_complex v603, v521+v522 ; bin: heap_oob 66 44 89 1c 18
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; asm: mov %cl,(%rax,%rbx,1)
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istore8_complex v600, v521+v522 ; bin: heap_oob 88 0c 18
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; asm: mov %cl,(%rax,%rbx,1)
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istore8_complex v601, v521+v522 ; bin: heap_oob 88 0c 18
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; asm: testq %rcx, %rcx
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; asm: je ebb1
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brz v1, ebb1 ; bin: 48 85 c9 74 1b
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@@ -158,9 +158,13 @@ ebb0(v1: i32):
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v6 = load.i64 aligned notrap v1
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v7 = load.i64 v1-12
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v8 = load.i64 notrap v1+0x1_0000
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v9 = load_complex.i64 v1+v2
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v10 = load_complex.i64 v1+v2+0x1
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store v2, v1
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store aligned v3, v1+12
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store notrap aligned v3, v1-12
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store_complex v3, v1+v2
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store_complex v3, v1+v2+0x1
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}
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; sameln: function %memory(i32) fast {
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; nextln: ebb0(v1: i32):
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@@ -171,9 +175,13 @@ ebb0(v1: i32):
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; nextln: v6 = load.i64 notrap aligned v1
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; nextln: v7 = load.i64 v1-12
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; nextln: v8 = load.i64 notrap v1+0x0001_0000
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; nextln: v9 = load_complex.i64 v1+v2
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; nextln: v10 = load_complex.i64 v1+v2+1
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; nextln: store v2, v1
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; nextln: store aligned v3, v1+12
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; nextln: store notrap aligned v3, v1-12
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; nextln: store_complex v3, v1+v2
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; nextln: store_complex v3, v1+v2+1
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; Register diversions.
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; This test file has no ISA, so we can unly use register unit numbers.
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95
cranelift/filetests/postopt/complex_memory_ops.cton
Normal file
95
cranelift/filetests/postopt/complex_memory_ops.cton
Normal file
@@ -0,0 +1,95 @@
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test postopt
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set is_64bit
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isa x86
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function %dual_loads(i64, i64) -> i64 {
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ebb0(v0: i64, v1: i64):
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[RexOp1rr#8001] v3 = iadd v0, v1
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v4 = load.i64 v3
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v5 = uload8.i64 v3
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v6 = sload8.i64 v3
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v7 = uload16.i64 v3
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v8 = sload16.i64 v3
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v9 = uload32.i64 v3
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v10 = sload32.i64 v3
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[Op1ret#c3] return v10
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}
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; sameln: function %dual_loads
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; nextln: ebb0(v0: i64, v1: i64):
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; nextln: v3 = iadd v0, v1
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; nextln: v4 = load_complex.i64 v0+v1
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; nextln: v5 = uload8_complex.i64 v0+v1
|
||||
; nextln: v6 = sload8_complex.i64 v0+v1
|
||||
; nextln: v7 = uload16_complex.i64 v0+v1
|
||||
; nextln: v8 = sload16_complex.i64 v0+v1
|
||||
; nextln: v9 = uload32_complex v0+v1
|
||||
; nextln: v10 = sload32_complex v0+v1
|
||||
; nextln: return v10
|
||||
; nextln: }
|
||||
|
||||
function %dual_loads2(i64, i64) -> i64 {
|
||||
ebb0(v0: i64, v1: i64):
|
||||
[RexOp1rr#8001] v3 = iadd v0, v1
|
||||
v4 = load.i64 v3+1
|
||||
v5 = uload8.i64 v3+1
|
||||
v6 = sload8.i64 v3+1
|
||||
v7 = uload16.i64 v3+1
|
||||
v8 = sload16.i64 v3+1
|
||||
v9 = uload32.i64 v3+1
|
||||
v10 = sload32.i64 v3+1
|
||||
[Op1ret#c3] return v10
|
||||
}
|
||||
|
||||
; sameln: function %dual_loads2
|
||||
; nextln: ebb0(v0: i64, v1: i64):
|
||||
; nextln: v3 = iadd v0, v1
|
||||
; nextln: v4 = load_complex.i64 v0+v1+1
|
||||
; nextln: v5 = uload8_complex.i64 v0+v1+1
|
||||
; nextln: v6 = sload8_complex.i64 v0+v1+1
|
||||
; nextln: v7 = uload16_complex.i64 v0+v1+1
|
||||
; nextln: v8 = sload16_complex.i64 v0+v1+1
|
||||
; nextln: v9 = uload32_complex v0+v1+1
|
||||
; nextln: v10 = sload32_complex v0+v1+1
|
||||
; nextln: return v10
|
||||
; nextln: }
|
||||
|
||||
function %dual_stores(i64, i64, i64) {
|
||||
ebb0(v0: i64, v1: i64, v2: i64):
|
||||
[RexOp1rr#8001] v3 = iadd v0, v1
|
||||
[RexOp1st#8089] store.i64 v2, v3
|
||||
[RexOp1st#88] istore8.i64 v2, v3
|
||||
[RexMp1st#189] istore16.i64 v2, v3
|
||||
[RexOp1st#89] istore32.i64 v2, v3
|
||||
[Op1ret#c3] return
|
||||
}
|
||||
|
||||
; sameln: function %dual_stores
|
||||
; nextln: ebb0(v0: i64, v1: i64, v2: i64):
|
||||
; nextln: v3 = iadd v0, v1
|
||||
; nextln: store_complex v2, v0+v1
|
||||
; nextln: istore8_complex v2, v0+v1
|
||||
; nextln: istore16_complex v2, v0+v1
|
||||
; nextln: istore32_complex v2, v0+v1
|
||||
; nextln: return
|
||||
; nextln: }
|
||||
|
||||
function %dual_stores2(i64, i64, i64) {
|
||||
ebb0(v0: i64, v1: i64, v2: i64):
|
||||
[RexOp1rr#8001] v3 = iadd v0, v1
|
||||
[RexOp1stDisp8#8089] store.i64 v2, v3+1
|
||||
[RexOp1stDisp8#88] istore8.i64 v2, v3+1
|
||||
[RexMp1stDisp8#189] istore16.i64 v2, v3+1
|
||||
[RexOp1stDisp8#89] istore32.i64 v2, v3+1
|
||||
[Op1ret#c3] return
|
||||
}
|
||||
|
||||
; sameln: function %dual_stores2
|
||||
; nextln: ebb0(v0: i64, v1: i64, v2: i64):
|
||||
; nextln: v3 = iadd v0, v1
|
||||
; nextln: store_complex v2, v0+v1+1
|
||||
; nextln: istore8_complex v2, v0+v1+1
|
||||
; nextln: istore16_complex v2, v0+v1+1
|
||||
; nextln: istore32_complex v2, v0+v1+1
|
||||
; nextln: return
|
||||
; nextln: }
|
||||
Reference in New Issue
Block a user