x64: port load to ISLE (#3993)
This change moves the majority of the lowerings for CLIF's `load` instruction over to ISLE. To do so, it also migrates the previous mechanism for creating an `Amode` (`lower_to_amode`) to several ISLE rules (see `to_amode`).
This commit is contained in:
Andrew Brown
@@ -748,18 +748,96 @@
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(decl put_in_reg_mem (Value) RegMem)
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(extern constructor put_in_reg_mem put_in_reg_mem)
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;; Addressing modes.
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(type SyntheticAmode extern (enum))
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(decl synthetic_amode_to_reg_mem (SyntheticAmode) RegMem)
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(extern constructor synthetic_amode_to_reg_mem synthetic_amode_to_reg_mem)
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(decl amode_to_synthetic_amode (Amode) SyntheticAmode)
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(extern constructor amode_to_synthetic_amode amode_to_synthetic_amode)
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(type Amode extern (enum))
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(decl amode_with_flags (Amode MemFlags) Amode)
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(extern constructor amode_with_flags amode_with_flags)
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(decl amode_imm_reg (u32 Gpr) Amode)
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(extern constructor amode_imm_reg amode_imm_reg)
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(decl amode_imm_reg_flags (u32 Gpr MemFlags) Amode)
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(rule (amode_imm_reg_flags offset base flags)
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(amode_with_flags (amode_imm_reg offset base) flags))
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(decl amode_imm_reg_reg_shift (u32 Gpr Gpr u8) Amode)
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(extern constructor amode_imm_reg_reg_shift amode_imm_reg_reg_shift)
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(decl amode_to_synthetic_amode (Amode) SyntheticAmode)
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(extern constructor amode_to_synthetic_amode amode_to_synthetic_amode)
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(decl amode_imm_reg_reg_shift_flags (u32 Gpr Gpr u8 MemFlags) Amode)
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(rule (amode_imm_reg_reg_shift_flags offset base index shift flags)
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(amode_with_flags (amode_imm_reg_reg_shift offset base index shift) flags))
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;; A helper to check if a shift amount (the `Value`) is both constant and
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;; less-than or equal to 3; this is needed since x64 can only shift addresses
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;; using two bits.
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(decl const_shift_lt_eq_3 (u8) Value)
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(extern extractor const_shift_lt_eq_3 const_shift_lt_eq_3 )
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;; A helper to both check that the `Imm64` and `Offset32` values sum to less
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;; than 32-bits AND return this summed `u32` value. Also, the `Imm64` will be
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;; zero-extended from `Type` up to 64 bits. This is useful for `to_amode`.
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(decl sum_extend_fits_in_32_bits (Type Imm64 u32) Offset32)
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(extern extractor sum_extend_fits_in_32_bits sum_extend_fits_in_32_bits (in in out))
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;; To generate an address for a memory access, we can pattern-match various CLIF
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;; sub-trees to x64's complex addressing modes (`Amode`). In pseudo-code:
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;;
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;; if address matches iadd(a, b):
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;; if either a or b:
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;; matches (ishl c with shift amount <= 3):
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;; amode(base + offset + (c << amount))
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;; matches (iconst c where c + offset will fit in 32 bits):
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;; amode(base + eval(c + offset))
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;; matches (uextend (iconst c) where c + offset will fit in 32 bits):
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;; amode(base + eval(c + offset))
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;; else:
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;; amode(a + offset + (b << 0))
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;; else:
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;; amode(base + offset)
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;;
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;; The rules for `to_amode` correspond to a subset of the possible addressing
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;; modes available by tweaking the SIB byte, the MOD bits, and the size of the
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;; displacement (i.e., offset). More information is available in Intel's
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;; Software Developer's Manual, volume 2, section 2.1.5, "Addressing-Mode
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;; Encoding of ModR/M and SIB Bytes."
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(decl to_amode (MemFlags Value Offset32) Amode)
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;; ...matches (ishl c ...)
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(rule (to_amode flags (iadd (ishl src (const_shift_lt_eq_3 amt)) base) offset)
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(amode_imm_reg_reg_shift_flags offset (put_in_gpr base) (put_in_gpr src) amt flags))
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(rule (to_amode flags (iadd base (ishl src (const_shift_lt_eq_3 amt))) offset)
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(amode_imm_reg_reg_shift_flags offset (put_in_gpr base) (put_in_gpr src) amt flags))
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;; ...matches (iconst c ...); note how this matching pattern uses an in-out
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;; extractor to check that the offset and constant value (`c`, the in
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;; parameter), when summed will fit into x64's 32-bit displacement, returned as
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;; `sum` (the out parameter). The syntax for this could be improved (TODO).
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(rule (to_amode flags (iadd (iconst c) base) _offset @ (sum_extend_fits_in_32_bits <$I64 <c sum))
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(amode_imm_reg_flags sum (put_in_gpr base) flags))
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(rule (to_amode flags (iadd base (iconst c)) _offset @ (sum_extend_fits_in_32_bits <$I64 <c sum))
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(amode_imm_reg_flags sum (put_in_gpr base) flags))
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;; ...matches (uextend(iconst c) ...); see notes above.
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(rule (to_amode flags (iadd (has_type ty (uextend (iconst c))) base) _offset @ (sum_extend_fits_in_32_bits <ty <c sum))
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(amode_imm_reg_flags sum (put_in_gpr base) flags))
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(rule (to_amode flags (iadd base (has_type ty (uextend (iconst c)))) _offset @ (sum_extend_fits_in_32_bits <ty <c sum))
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(amode_imm_reg_flags sum (put_in_gpr base) flags))
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;; ...else only matches (iadd(a b))
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(rule (to_amode flags (iadd base index) offset)
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(amode_imm_reg_reg_shift_flags offset (put_in_gpr base) (put_in_gpr index) 0 flags))
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;; ...else
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(rule (to_amode flags base offset)
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(amode_imm_reg_flags offset (put_in_gpr base) flags))
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;; Shift kinds.
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(type ShiftKind extern
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(enum ShiftLeft
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@@ -1152,11 +1230,11 @@
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;; Zero extending uses `movzx`.
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(rule (extend (ExtendKind.Zero) ty mode src)
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(x64_movzx ty mode src))
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(x64_movzx mode src))
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;; Sign extending uses `movsx`.
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(rule (extend (ExtendKind.Sign) ty mode src)
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(x64_movsx ty mode src))
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(x64_movsx mode src))
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;;;; Helpers for Working SSE tidbits ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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@@ -1235,8 +1313,7 @@
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(decl x64_load (Type SyntheticAmode ExtKind) Reg)
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(rule (x64_load (fits_in_32 ty) addr (ExtKind.SignExtend))
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(x64_movsx ty
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(ext_mode (ty_bytes ty) 8)
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(x64_movsx (ext_mode (ty_bytes ty) 8)
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addr))
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(rule (x64_load $I64 addr _ext_kind)
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@@ -1264,6 +1341,68 @@
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(xmm_unary_rm_r (SseOpcode.Movdqu)
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addr))
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(decl x64_mov (Amode) Reg)
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(rule (x64_mov addr)
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(let ((dst WritableGpr (temp_writable_gpr))
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(_ Unit (emit (MInst.Mov64MR addr dst))))
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dst))
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(decl x64_movzx (ExtMode GprMem) Gpr)
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(rule (x64_movzx mode src)
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(let ((dst WritableGpr (temp_writable_gpr))
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(_ Unit (emit (MInst.MovzxRmR mode src dst))))
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dst))
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(decl x64_movsx (ExtMode GprMem) Gpr)
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(rule (x64_movsx mode src)
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(let ((dst WritableGpr (temp_writable_gpr))
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(_ Unit (emit (MInst.MovsxRmR mode src dst))))
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dst))
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(decl x64_movss_load (XmmMem) Xmm)
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(rule (x64_movss_load from)
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(xmm_unary_rm_r (SseOpcode.Movss) from))
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(decl x64_movsd_load (XmmMem) Xmm)
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(rule (x64_movsd_load from)
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(xmm_unary_rm_r (SseOpcode.Movsd) from))
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(decl x64_movups (XmmMem) Xmm)
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(rule (x64_movups from)
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(xmm_unary_rm_r (SseOpcode.Movups) from))
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(decl x64_movupd (XmmMem) Xmm)
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(rule (x64_movupd from)
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(xmm_unary_rm_r (SseOpcode.Movupd) from))
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(decl x64_movdqu (XmmMem) Xmm)
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(rule (x64_movdqu from)
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(xmm_unary_rm_r (SseOpcode.Movdqu) from))
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(decl x64_pmovsxbw (XmmMem) Xmm)
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(rule (x64_pmovsxbw from)
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(xmm_unary_rm_r (SseOpcode.Pmovsxbw) from))
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(decl x64_pmovzxbw (XmmMem) Xmm)
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(rule (x64_pmovzxbw from)
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(xmm_unary_rm_r (SseOpcode.Pmovzxbw) from))
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(decl x64_pmovsxwd (XmmMem) Xmm)
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(rule (x64_pmovsxwd from)
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(xmm_unary_rm_r (SseOpcode.Pmovsxwd) from))
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(decl x64_pmovzxwd (XmmMem) Xmm)
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(rule (x64_pmovzxwd from)
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(xmm_unary_rm_r (SseOpcode.Pmovzxwd) from))
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(decl x64_pmovsxdq (XmmMem) Xmm)
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(rule (x64_pmovsxdq from)
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(xmm_unary_rm_r (SseOpcode.Pmovsxdq) from))
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(decl x64_pmovzxdq (XmmMem) Xmm)
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(rule (x64_pmovzxdq from)
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(xmm_unary_rm_r (SseOpcode.Pmovzxdq) from))
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;; Load a constant into an XMM register.
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(decl x64_xmm_load_const (Type VCodeConstant) Xmm)
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(rule (x64_xmm_load_const ty const)
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@@ -1665,20 +1804,6 @@
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(MInst.Setcc cc dst)
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dst)))
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;; Helper for creating `MInst.MovzxRmR` instructions.
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(decl x64_movzx (Type ExtMode GprMem) Gpr)
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(rule (x64_movzx ty mode src)
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(let ((dst WritableGpr (temp_writable_gpr))
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(_ Unit (emit (MInst.MovzxRmR mode src dst))))
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dst))
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;; Helper for creating `MInst.MovsxRmR` instructions.
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(decl x64_movsx (Type ExtMode GprMem) Gpr)
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(rule (x64_movsx ty mode src)
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(let ((dst WritableGpr (temp_writable_gpr))
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(_ Unit (emit (MInst.MovsxRmR mode src dst))))
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dst))
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;; Helper for creating `MInst.XmmRmR` instructions.
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(decl xmm_rm_r (Type SseOpcode Xmm XmmMem) Xmm)
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(rule (xmm_rm_r ty op src1 src2)
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@@ -1995,8 +2120,8 @@
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(xmm_rm_r $F64X2 (SseOpcode.Blendvpd) src1 src2)))
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;; Helper for creating `movsd` instructions.
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(decl x64_movsd (Xmm XmmMem) Xmm)
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(rule (x64_movsd src1 src2)
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(decl x64_movsd_regmove (Xmm XmmMem) Xmm)
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(rule (x64_movsd_regmove src1 src2)
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(xmm_rm_r $I8X16 (SseOpcode.Movsd) src1 src2))
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;; Helper for creating `movlhps` instructions.
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@@ -2191,16 +2316,6 @@
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(_ Unit (emit (MInst.XmmUnaryRmR op src dst))))
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dst))
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;; Helper for creating `pmovsxbw` instructions.
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(decl x64_pmovsxbw (XmmMem) Xmm)
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(rule (x64_pmovsxbw src)
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(xmm_unary_rm_r (SseOpcode.Pmovsxbw) src))
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;; Helper for creating `pmovzxbw` instructions.
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(decl x64_pmovzxbw (XmmMem) Xmm)
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(rule (x64_pmovzxbw src)
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(xmm_unary_rm_r (SseOpcode.Pmovzxbw) src))
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;; Helper for creating `pabsb` instructions.
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(decl x64_pabsb (XmmMem) Xmm)
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(rule (x64_pabsb src)
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@@ -2582,7 +2697,9 @@
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(convert Imm8Reg Imm8Gpr imm8_reg_to_imm8_gpr)
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(convert Amode SyntheticAmode amode_to_synthetic_amode)
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(convert Amode GprMem amode_to_gpr_mem)
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(convert SyntheticAmode GprMem synthetic_amode_to_gpr_mem)
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(convert Amode XmmMem amode_to_xmm_mem)
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(convert SyntheticAmode XmmMem synthetic_amode_to_xmm_mem)
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(convert IntCC CC intcc_to_cc)
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@@ -2614,8 +2731,14 @@
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(value_reg w_xmm))
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(decl synthetic_amode_to_gpr_mem (SyntheticAmode) GprMem)
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(decl amode_to_gpr_mem (Amode) GprMem)
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(rule (amode_to_gpr_mem amode)
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(amode_to_synthetic_amode amode))
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(rule (synthetic_amode_to_gpr_mem amode)
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(synthetic_amode_to_reg_mem amode))
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(decl amode_to_xmm_mem (Amode) XmmMem)
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(rule (amode_to_xmm_mem amode)
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(amode_to_synthetic_amode amode))
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(decl synthetic_amode_to_xmm_mem (SyntheticAmode) XmmMem)
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(rule (synthetic_amode_to_xmm_mem amode)
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(synthetic_amode_to_reg_mem amode))
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