Rename Cretonne to Cranelift!

lib/codegen/meta/isa/__init__.py

@@ -1,9 +1,9 @@
 """
-Cretonne target ISA definitions
--------------------------------
+Cranelift target ISA definitions
+--------------------------------
 
 The :py:mod:`isa` package contains sub-packages for each target instruction set
-architecture supported by Cretonne.
+architecture supported by Cranelift.
 """
 from __future__ import absolute_import
 from cdsl.isa import TargetISA  # noqa
@@ -19,6 +19,6 @@ def all_isas():
     # type: () -> List[TargetISA]
     """
     Get a list of all the supported target ISAs. Each target ISA is represented
-    as a :py:class:`cretonne.TargetISA` instance.
+    as a :py:class:`cranelift.TargetISA` instance.
     """
     return [riscv.ISA, x86.ISA, arm32.ISA, arm64.ISA]

lib/codegen/meta/isa/riscv/encodings.py

@@ -61,7 +61,7 @@ RV32.enc(base.iconst.i32, Iz, OPIMM(0b000))
 RV64.enc(base.iconst.i32, Iz, OPIMM(0b000))
 RV64.enc(base.iconst.i64, Iz, OPIMM(0b000))
 
-# Dynamic shifts have the same masking semantics as the cton base instructions.
+# Dynamic shifts have the same masking semantics as the clif base instructions.
 for inst,           inst_imm,      f3,    f7 in [
         (base.ishl, base.ishl_imm, 0b001, 0b0000000),
         (base.ushr, base.ushr_imm, 0b101, 0b0000000),

lib/codegen/meta/isa/x86/__init__.py

@@ -1,12 +1,12 @@
 """
 x86 Target Architecture
--------------------------
+-----------------------
 
 This target ISA generates code for x86 CPUs with two separate CPU modes:
 
 `I32`
     32-bit x86 architecture, also known as 'IA-32', also sometimes referred
-    to as 'i386', however note that Cretonne depends on instructions not
+    to as 'i386', however note that Cranelift depends on instructions not
     in the original `i386`, such as SSE2, CMOVcc, and UD2.
 
 `I64`

lib/codegen/meta/isa/x86/recipes.py

@@ -34,7 +34,7 @@ except ImportError:
 
 # Opcode representation.
 #
-# Cretonne requires each recipe to have a single encoding size in bytes, and
+# Cranelift requires each recipe to have a single encoding size in bytes, and
 # x86 opcodes are variable length, so we use separate recipes for different
 # styles of opcodes and prefixes. The opcode format is indicated by the recipe
 # name prefix:
@@ -1600,7 +1600,7 @@ rcmp_sp = TailRecipe(
 #
 # 1. Guarantee that the test and branch get scheduled next to each other so
 #    macro fusion is guaranteed to be possible.
-# 2. Hide the status flags from Cretonne which doesn't currently model flags.
+# 2. Hide the status flags from Cranelift which doesn't currently model flags.
 #
 # The encoding bits affect both the test and the branch instruction:
 #