Rename Cretonne to Cranelift!

cranelift/filetests/postopt/basic.clif

@@ -0,0 +1,100 @@
+test postopt
+target i686
+
+; Test that compare+branch sequences are folded effectively on x86.
+
+function %br_icmp(i32, i32) -> i32 {
+ebb0(v0: i32, v1: i32):
+[Op1icscc#39,%rdx]  v2 = icmp slt v0, v1
+[Op1t8jccd_long#85] brnz v2, ebb1
+[Op1ret#c3]         return v1
+
+ebb1:
+[Op1pu_id#b8,%rax]  v8 = iconst.i32 3
+[Op1ret#c3]         return v8
+}
+; sameln: function %br_icmp
+; nextln: ebb0(v0: i32, v1: i32):
+; nextln:    v9 = ifcmp v0, v1
+; nextln:    v2 = trueif slt v9
+; nextln:    brif slt v9, ebb1
+; nextln:    return v1
+; nextln: 
+; nextln: ebb1:
+; nextln:    v8 = iconst.i32 3
+; nextln:    return v8
+; nextln: }
+
+; Use brz instead of brnz, so the condition is inverted.
+
+function %br_icmp_inverse(i32, i32) -> i32 {
+ebb0(v0: i32, v1: i32):
+[Op1icscc#39,%rdx]  v2 = icmp slt v0, v1
+[Op1t8jccd_long#84] brz v2, ebb1
+[Op1ret#c3]         return v1
+
+ebb1:
+[Op1pu_id#b8,%rax]  v8 = iconst.i32 3
+[Op1ret#c3]         return v8
+}
+; sameln: function %br_icmp_inverse
+; nextln: ebb0(v0: i32, v1: i32):
+; nextln:    v9 = ifcmp v0, v1
+; nextln:    v2 = trueif slt v9
+; nextln:    brif sge v9, ebb1
+; nextln:    return v1
+; nextln: 
+; nextln: ebb1:
+; nextln:    v8 = iconst.i32 3
+; nextln:    return v8
+; nextln: }
+
+; Use icmp_imm instead of icmp.
+
+function %br_icmp_imm(i32, i32) -> i32 {
+ebb0(v0: i32, v1: i32):
+[Op1icscc_ib#7083]  v2 = icmp_imm slt v0, 2
+[Op1t8jccd_long#84] brz v2, ebb1
+[Op1ret#c3]         return v1
+
+ebb1:
+[Op1pu_id#b8,%rax]  v8 = iconst.i32 3
+[Op1ret#c3]         return v8
+}
+; sameln: function %br_icmp_imm
+; nextln: ebb0(v0: i32, v1: i32):
+; nextln:    v9 = ifcmp_imm v0, 2
+; nextln:    v2 = trueif slt v9
+; nextln:    brif sge v9, ebb1
+; nextln:    return v1
+; nextln: 
+; nextln: ebb1:
+; nextln:    v8 = iconst.i32 3
+; nextln:    return v8
+; nextln: }
+
+; Use fcmp instead of icmp.
+
+function %br_fcmp(f32, f32) -> f32 {
+ebb0(v0: f32, v1: f32):
+[Op2fcscc#42e,%rdx] v2 = fcmp gt v0, v1
+[Op1t8jccd_long#84] brz v2, ebb1
+[Op1ret#c3]         return v1
+
+ebb1:
+[Op1pu_id#b8,%rax]   v18 = iconst.i32 0x40a8_0000
+[Mp2frurm#56e,%xmm0] v8 = bitcast.f32 v18
+[Op1ret#c3]         return v8
+}
+; sameln: function %br_fcmp
+; nextln: ebb0(v0: f32, v1: f32):
+; nextln:    v19 = ffcmp v0, v1
+; nextln:    v2 = trueff gt v19
+; nextln:    brff ule v19, ebb1
+; nextln:    return v1
+; nextln: 
+; nextln: ebb1:
+; nextln:    v18 = iconst.i32 0x40a8_0000
+; nextln:    v8 = bitcast.f32 v18
+; nextln:    return v8
+; nextln: }