Rename Cretonne to Cranelift!

2018-07-13 09:01:28 -07:00
parent 19a636af96
commit f4dbd38a4c
306 changed files with 977 additions and 975 deletions
--- a/cranelift/filetests/isa/x86/binary64-pic.clif
+++ b/cranelift/filetests/isa/x86/binary64-pic.clif
@@ -0,0 +1,83 @@
+; binary emission of 64-bit code.
+test binemit
+set opt_level=best
+set is_pic
+target x86_64 haswell
+
+; The binary encodings can be verified with the command:
+;
+;   sed -ne 's/^ *; asm: *//p' filetests/isa/x86/binary64-pic.clif | llvm-mc -show-encoding -triple=x86_64
+;
+
+; Tests for i64 instructions.
+function %I64() {
+    sig0 = ()
+    fn0 = %foo()
+    fn1 = colocated %bar()
+
+    gv0 = globalsym %some_gv
+    gv1 = globalsym colocated %some_gv
+
+    ; Use incoming_arg stack slots because they won't be relocated by the frame
+    ; layout.
+    ss0 = incoming_arg 8, offset 0
+    ss1 = incoming_arg 1024, offset -1024
+    ss2 = incoming_arg 1024, offset -2048
+    ss3 = incoming_arg 8, offset -2056
+
+ebb0:
+
+    ; Colocated functions.
+
+    ; asm: call foo
+    call fn1()                                  ; bin: stk_ovf e8 CallPCRel4(%bar-4) 00000000
+
+    ; asm: lea 0x0(%rip), %rax
+    [-,%rax]            v0 = func_addr.i64 fn1        ; bin: 48 8d 05 PCRel4(%bar-4) 00000000
+    ; asm: lea 0x0(%rip), %rsi
+    [-,%rsi]            v1 = func_addr.i64 fn1        ; bin: 48 8d 35 PCRel4(%bar-4) 00000000
+    ; asm: lea 0x0(%rip), %r10
+    [-,%r10]            v2 = func_addr.i64 fn1        ; bin: 4c 8d 15 PCRel4(%bar-4) 00000000
+
+    ; asm: call *%rax
+    call_indirect sig0, v0()                  ; bin: stk_ovf ff d0
+    ; asm: call *%rsi
+    call_indirect sig0, v1()                  ; bin: stk_ovf ff d6
+    ; asm: call *%r10
+    call_indirect sig0, v2()                  ; bin: stk_ovf 41 ff d2
+
+    ; Non-colocated functions.
+
+    ; asm: call foo@PLT
+    call fn0()                                  ; bin: stk_ovf e8 CallPLTRel4(%foo-4) 00000000
+
+    ; asm: mov 0x0(%rip), %rax
+    [-,%rax]            v100 = func_addr.i64 fn0        ; bin: 48 8b 05 GOTPCRel4(%foo-4) 00000000
+    ; asm: mov 0x0(%rip), %rsi
+    [-,%rsi]            v101 = func_addr.i64 fn0        ; bin: 48 8b 35 GOTPCRel4(%foo-4) 00000000
+    ; asm: mov 0x0(%rip), %r10
+    [-,%r10]            v102 = func_addr.i64 fn0        ; bin: 4c 8b 15 GOTPCRel4(%foo-4) 00000000
+
+    ; asm: call *%rax
+    call_indirect sig0, v100()                  ; bin: stk_ovf ff d0
+    ; asm: call *%rsi
+    call_indirect sig0, v101()                  ; bin: stk_ovf ff d6
+    ; asm: call *%r10
+    call_indirect sig0, v102()                  ; bin: stk_ovf 41 ff d2
+
+    ; asm: mov 0x0(%rip), %rcx
+    [-,%rcx]            v3 = globalsym_addr.i64 gv0    ; bin: 48 8b 0d GOTPCRel4(%some_gv-4) 00000000
+    ; asm: mov 0x0(%rip), %rsi
+    [-,%rsi]            v4 = globalsym_addr.i64 gv0    ; bin: 48 8b 35 GOTPCRel4(%some_gv-4) 00000000
+    ; asm: mov 0x0(%rip), %r10
+    [-,%r10]            v5 = globalsym_addr.i64 gv0    ; bin: 4c 8b 15 GOTPCRel4(%some_gv-4) 00000000
+
+    ; asm: lea 0x0(%rip), %rcx
+    [-,%rcx]            v6 = globalsym_addr.i64 gv1    ; bin: 48 8d 0d PCRel4(%some_gv-4) 00000000
+    ; asm: lea 0x0(%rip), %rsi
+    [-,%rsi]            v7 = globalsym_addr.i64 gv1    ; bin: 48 8d 35 PCRel4(%some_gv-4) 00000000
+    ; asm: lea 0x0(%rip), %r10
+    [-,%r10]            v8 = globalsym_addr.i64 gv1    ; bin: 4c 8d 15 PCRel4(%some_gv-4) 00000000
+
+    return
+}