cranelift: Implement sqrt in interpreter (#4362)

This ignores SIMD for now.

cranelift/filetests/filetests/runtests/sqrt.clif

@@ -0,0 +1,97 @@
+test interpret
+test run
+target aarch64
+target x86_64
+target s390x
+
+function %sqrt_f32(f32) -> f32 {
+block0(v0: f32):
+    v1 = sqrt v0
+    return v1
+}
+; run: %sqrt_f32(0x9.0) == 0x3.0
+; run: %sqrt_f32(0x0.0) == 0x0.0
+; run: %sqrt_f32(-0x0.0) == -0x0.0
+; run: %sqrt_f32(+Inf) == +Inf
+
+; F32 Epsilon  / Max / Min Positive
+; run: %sqrt_f32(0x1.000000p-23) == 0x1.6a09e6p-12
+; run: %sqrt_f32(0x1.fffffep127) == 0x1.fffffep63
+; run: %sqrt_f32(0x1.000000p-126) == 0x1.000000p-63
+
+; F32 Subnormals
+; run: %sqrt_f32(0x0.800000p-126) == 0x1.6a09e6p-64
+; run: %sqrt_f32(0x0.000002p-126) == 0x1.6a09e6p-75
+
+
+; The IEEE754 Standard does not make a lot of guarantees about what
+; comes out of NaN producing operations, we just check if its a NaN
+function %sqrt_is_nan_f32(f32) -> i32 {
+block0(v0: f32):
+    v2 = sqrt v0
+    v3 = fcmp ne v2, v2
+    v4 = bint.i32 v3
+    return v4
+}
+; run: %sqrt_is_nan_f32(-0x9.0) == 1
+; run: %sqrt_is_nan_f32(-Inf) == 1
+; run: %sqrt_is_nan_f32(+NaN) == 1
+; run: %sqrt_is_nan_f32(-NaN) == 1
+; run: %sqrt_is_nan_f32(+NaN:0x0) == 1
+; run: %sqrt_is_nan_f32(+NaN:0x1) == 1
+; run: %sqrt_is_nan_f32(+NaN:0x300001) == 1
+; run: %sqrt_is_nan_f32(-NaN:0x0) == 1
+; run: %sqrt_is_nan_f32(-NaN:0x1) == 1
+; run: %sqrt_is_nan_f32(-NaN:0x300001) == 1
+; run: %sqrt_is_nan_f32(+sNaN:0x1) == 1
+; run: %sqrt_is_nan_f32(-sNaN:0x1) == 1
+; run: %sqrt_is_nan_f32(+sNaN:0x200001) == 1
+; run: %sqrt_is_nan_f32(-sNaN:0x200001) == 1
+; run: %sqrt_is_nan_f32(-0x1.fffffep127) == 1
+
+
+
+function %sqrt_f64(f64) -> f64 {
+block0(v0: f64):
+    v1 = sqrt v0
+    return v1
+}
+; run: %sqrt_f64(0x9.0) == 0x3.0
+; run: %sqrt_f64(0x0.0) == 0x0.0
+; run: %sqrt_f64(-0x0.0) == -0x0.0
+; run: %sqrt_f64(+Inf) == +Inf
+
+; F64 Epsilon / Max / Min Positive
+; run: %sqrt_f64(0x1.0000000000000p-52) == 0x1.0000000000000p-26
+; run: %sqrt_f64(0x1.fffffffffffffp1023) == 0x1.fffffffffffffp511
+; run: %sqrt_f64(0x1.0000000000000p-1022) == 0x1.0000000000000p-511
+
+; F64 Subnormals
+; run: %sqrt_f64(0x0.8000000000000p-1022) == 0x1.6a09e667f3bcdp-512
+; run: %sqrt_f64(0x0.0000000000001p-1022) == 0x1.0000000000000p-537
+
+
+; The IEEE754 Standard does not make a lot of guarantees about what
+; comes out of NaN producing operations, we just check if its a NaN
+function %sqrt_is_nan_f64(f64) -> i32 {
+block0(v0: f64):
+    v2 = sqrt v0
+    v3 = fcmp ne v2, v2
+    v4 = bint.i32 v3
+    return v4
+}
+; run: %sqrt_is_nan_f64(-0x9.0) == 1
+; run: %sqrt_is_nan_f64(-Inf) == 1
+; run: %sqrt_is_nan_f64(+NaN) == 1
+; run: %sqrt_is_nan_f64(-NaN) == 1
+; run: %sqrt_is_nan_f64(+NaN:0x0) == 1
+; run: %sqrt_is_nan_f64(+NaN:0x1) == 1
+; run: %sqrt_is_nan_f64(+NaN:0x4000000000001) == 1
+; run: %sqrt_is_nan_f64(-NaN:0x0) == 1
+; run: %sqrt_is_nan_f64(-NaN:0x1) == 1
+; run: %sqrt_is_nan_f64(-NaN:0x4000000000001) == 1
+; run: %sqrt_is_nan_f64(+sNaN:0x1) == 1
+; run: %sqrt_is_nan_f64(-sNaN:0x1) == 1
+; run: %sqrt_is_nan_f64(+sNaN:0x4000000000001) == 1
+; run: %sqrt_is_nan_f64(-sNaN:0x4000000000001) == 1
+; run: %sqrt_is_nan_f64(-0x1.fffffffffffffp1023) == 1