Adds support for signed packed integer conversion to float
f32x4.convert_i32x4_s
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@@ -2141,28 +2141,41 @@ fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
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}
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Opcode::FcvtFromSint => {
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let (ext_spec, src_size) = match ctx.input_ty(insn, 0) {
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types::I8 | types::I16 => (Some(ExtSpec::SignExtendTo32), OperandSize::Size32),
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types::I32 => (None, OperandSize::Size32),
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types::I64 => (None, OperandSize::Size64),
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_ => unreachable!(),
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};
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let src = match ext_spec {
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Some(ext_spec) => RegMem::reg(extend_input_to_reg(ctx, inputs[0], ext_spec)),
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None => input_to_reg_mem(ctx, inputs[0]),
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};
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let output_ty = ty.unwrap();
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let opcode = if output_ty == types::F32 {
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SseOpcode::Cvtsi2ss
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} else {
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assert_eq!(output_ty, types::F64);
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SseOpcode::Cvtsi2sd
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};
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if !output_ty.is_vector() {
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let (ext_spec, src_size) = match ctx.input_ty(insn, 0) {
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types::I8 | types::I16 => (Some(ExtSpec::SignExtendTo32), OperandSize::Size32),
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types::I32 => (None, OperandSize::Size32),
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types::I64 => (None, OperandSize::Size64),
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_ => unreachable!(),
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};
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let dst = get_output_reg(ctx, outputs[0]);
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ctx.emit(Inst::gpr_to_xmm(opcode, src, src_size, dst));
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let src = match ext_spec {
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Some(ext_spec) => RegMem::reg(extend_input_to_reg(ctx, inputs[0], ext_spec)),
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None => input_to_reg_mem(ctx, inputs[0]),
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};
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let opcode = if output_ty == types::F32 {
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SseOpcode::Cvtsi2ss
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} else {
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assert_eq!(output_ty, types::F64);
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SseOpcode::Cvtsi2sd
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};
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let dst = get_output_reg(ctx, outputs[0]);
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ctx.emit(Inst::gpr_to_xmm(opcode, src, src_size, dst));
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} else {
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let ty = ty.unwrap();
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let src = put_input_in_reg(ctx, inputs[0]);
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let dst = get_output_reg(ctx, outputs[0]);
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let opcode = match ctx.input_ty(insn, 0) {
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types::I32X4 => SseOpcode::Cvtdq2ps,
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_ => {
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unimplemented!("unable to use type {} for op {}", ctx.input_ty(insn, 0), op)
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}
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};
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ctx.emit(Inst::gen_move(dst, src, ty));
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ctx.emit(Inst::xmm_rm_r(opcode, RegMem::from(dst), dst));
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}
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}
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Opcode::FcvtFromUint => {
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