Bump regalloc2 to 0.5.0 (#5345)
* Bump the regalloc2 dependency to 0.5.0 * Replace preg_set_from_machine_env with PRegSet::from * Vet the regalloc2 update
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@@ -25,7 +25,7 @@ use regalloc2::{MachineEnv, PRegSet};
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use smallvec::{smallvec, SmallVec};
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use std::fmt::Debug;
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use super::{preg_set_from_machine_env, VCodeBuildDirection, VRegAllocator};
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use super::{VCodeBuildDirection, VRegAllocator};
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/// An "instruction color" partitions CLIF instructions by side-effecting ops.
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/// All instructions with the same "color" are guaranteed not to be separated by
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@@ -417,7 +417,7 @@ impl<'func, I: VCodeInst> Lower<'func, I> {
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Ok(Lower {
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f,
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flags,
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allocatable: preg_set_from_machine_env(machine_env),
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allocatable: PRegSet::from(machine_env),
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vcode,
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vregs,
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value_regs,
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@@ -4,7 +4,7 @@
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use alloc::{string::String, vec::Vec};
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use core::{fmt::Debug, hash::Hash};
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use regalloc2::{Allocation, MachineEnv, Operand, OperandConstraint, PReg, PRegSet, VReg};
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use regalloc2::{Allocation, Operand, OperandConstraint, PReg, PRegSet, VReg};
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#[cfg(feature = "enable-serde")]
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use serde::{Deserialize, Serialize};
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@@ -38,26 +38,6 @@ pub fn first_user_vreg_index() -> usize {
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PINNED_VREGS
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}
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/// Collect the registers from a regalloc2 MachineEnv into a PRegSet.
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/// TODO: remove this once it's upstreamed in regalloc2
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pub fn preg_set_from_machine_env(machine_env: &MachineEnv) -> PRegSet {
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let mut regs = PRegSet::default();
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for class in machine_env.preferred_regs_by_class.iter() {
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for reg in class.iter() {
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regs.add(*reg);
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}
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}
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for class in machine_env.non_preferred_regs_by_class.iter() {
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for reg in class.iter() {
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regs.add(*reg);
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}
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}
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regs
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}
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/// A register named in an instruction. This register can be either a
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/// virtual register or a fixed physical register. It does not have
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/// any constraints applied to it: those can be added later in
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