Add initial SIMD memory filetests

cranelift/filetests/filetests/isa/x86/simd-memory-binemit.clif

@@ -0,0 +1,37 @@
+test binemit
+set enable_simd
+target x86_64 skylake
+
+function %load_store_simple(i64) {
+block0(v0: i64 [%rax]):
+[-, %xmm0]    v10 = load.i32x4 v0   ; bin: heap_oob 0f 10 00
+[-]           store v10, v0         ; bin: heap_oob 0f 11 00
+
+              ; use displacement
+[-, %xmm0]    v11 = load.f32x4 v0+42 ; bin: heap_oob 0f 10 40 2a
+[-]           store v11, v0+42       ; bin: heap_oob 0f 11 40 2a
+
+              ; use REX prefix
+[-, %xmm8]    v12 = load.i8x16 v0   ; bin: heap_oob 44 0f 10 00
+[-]           store v12, v0         ; bin: heap_oob 44 0f 11 00
+
+    return
+}
+
+function %load_store_complex(i64, i64) {
+block0(v0: i64 [%rax], v1: i64 [%rbx]):
+              ; %xmm1 corresponds to ModR/M 0x04; the 0b100 in the R/M slot indicates a SIB byte follows
+              ; %rax and %rbx form the SIB 0x18
+[-, %xmm1]    v10 = load_complex.f64x2 v0+v1   ; bin: heap_oob 0f 10 0c 18
+              ; enabling bit 6 of the ModR/M byte indicates a disp8 follows
+[-]           store_complex v10, v0+v1+5       ; bin: heap_oob 0f 11 4c 18 05
+
+    return
+}
+
+function %copy_to_ssa() {
+block0:
+[-, %xmm1]    v0 = copy_to_ssa.i64x2 %xmm3  ; bin: 0f 28 cb
+
+    return
+}