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Simplify LowerBackend interface (#5432)

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* Refactor lower_branch to have Unit result

Branches cannot have any output, so it is more straightforward
to have the ISLE term return Unit instead of InstOutput.

Also provide a new `emit_side_effect` term to simplify
implementation of `lower_branch` rules with Unit result.

* Simplify LowerBackend interface

Move all remaining asserts from the LowerBackend::lower and
::lower_branch_group into the common call site.

Change return value of ::lower to Option<InstOutput>, and
return value of ::lower_branch_group to Option<()> to match
ISLE term signature.

Only pass the first branch into ::lower_branch_group and
rename it to ::lower_branch.

As a result of all those changes, LowerBackend routines
now consists solely to calls to the corresponding ISLE
routines.
This commit is contained in:
Ulrich Weigand
2022-12-14 01:48:25 +01:00
committed by GitHub
parent 299be327d5
commit f0af622208
16 changed files with 133 additions and 244 deletions
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14
cranelift/codegen/src/isa/riscv64/lower/isle.rs
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@@ -68,7 +68,7 @@ impl generated_code::Context for IsleContext<'_, '_, MInst, Riscv64Backend> {
b: Reg,
targets: &VecMachLabel,
ty: Type,
) -> InstOutput {
) -> Unit {
let tmp = self.temp_writable_reg(I64);
MInst::lower_br_fcmp(
*cc,
@@ -81,7 +81,6 @@ impl generated_code::Context for IsleContext<'_, '_, MInst, Riscv64Backend> {
)
.iter()
.for_each(|i| self.emit(i));
InstOutput::default()
}
fn lower_brz_or_nz(
@@ -90,7 +89,7 @@ impl generated_code::Context for IsleContext<'_, '_, MInst, Riscv64Backend> {
a: ValueRegs,
targets: &VecMachLabel,
ty: Type,
) -> InstOutput {
) -> Unit {
MInst::lower_br_icmp(
*cc,
a,
@@ -101,7 +100,6 @@ impl generated_code::Context for IsleContext<'_, '_, MInst, Riscv64Backend> {
)
.iter()
.for_each(|i| self.emit(i));
InstOutput::default()
}
fn lower_br_icmp(
&mut self,
@@ -110,7 +108,7 @@ impl generated_code::Context for IsleContext<'_, '_, MInst, Riscv64Backend> {
b: ValueRegs,
targets: &VecMachLabel,
ty: Type,
) -> InstOutput {
) -> Unit {
let test = generated_code::constructor_lower_icmp(self, cc, a, b, ty);
self.emit(&MInst::CondBr {
taken: BranchTarget::Label(targets[0]),
@@ -121,7 +119,6 @@ impl generated_code::Context for IsleContext<'_, '_, MInst, Riscv64Backend> {
rs2: zero_reg(),
},
});
InstOutput::default()
}
fn load_ra(&mut self) -> Reg {
if self.backend.flags.preserve_frame_pointers() {
@@ -397,7 +394,7 @@ impl generated_code::Context for IsleContext<'_, '_, MInst, Riscv64Backend> {
tmp.to_reg()
}
fn lower_br_table(&mut self, index: Reg, targets: &VecMachLabel) -> InstOutput {
fn lower_br_table(&mut self, index: Reg, targets: &VecMachLabel) -> Unit {
let tmp1 = self.temp_writable_reg(I64);
let targets: Vec<BranchTarget> = targets
.into_iter()
@@ -409,7 +406,6 @@ impl generated_code::Context for IsleContext<'_, '_, MInst, Riscv64Backend> {
tmp1,
targets,
});
InstOutput::default()
}
fn x_reg(&mut self, x: u8) -> Reg {
x_reg(x as usize)
@@ -446,7 +442,7 @@ pub(crate) fn lower_branch(
backend: &Riscv64Backend,
branch: Inst,
targets: &[MachLabel],
) -> Option<InstOutput> {
) -> Option<()> {
// TODO: reuse the ISLE context across lowerings so we can reuse its
// internal heap allocations.
let mut isle_ctx = IsleContext { lower_ctx, backend };