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x64: remove Inst::XmmLoadConst (#4876)

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This is a cherry-pick of a long-ago commit, 2d46637. The original
message reads:

> Now that `SyntheticAmode` can refer to constants, there is no longer a
> need for a separate instruction format--standard load instructions will
> work.

Since then, the transition to ISLE and the use of `XmmLoadConst` in many
more places makes this change a larger diff than the original. The basic
idea is the same, though: the extra indirection of `Inst::XMmLoadConst`
is removed and replaced by a direct use of `VCodeConstant` as a
`SyntheticAmode`. This has no effect on codegen, but the CLIF output is
now clearer in that the actual instruction is displayed (e.g., `movdqu`)
instead of a made-up instruction (`load_const`).
This commit is contained in:
Andrew Brown
2022-09-07 12:52:13 -07:00
committed by GitHub
parent e694a6f5d4
commit f063082474
14 changed files with 53 additions and 61 deletions
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4
cranelift/filetests/filetests/isa/x64/fcvt.clif
View File

@@ -170,9 +170,9 @@ block0(v0: i32x4):
; pushq %rbp
; movq %rsp, %rbp
; block0:
; load_const VCodeConstant(0), %xmm3
; movdqu const(0), %xmm3
; unpcklps %xmm0, %xmm3, %xmm0
; load_const VCodeConstant(1), %xmm7
; movdqu const(1), %xmm7
; subpd %xmm0, %xmm7, %xmm0
; movq %rbp, %rsp
; popq %rbp

8
cranelift/filetests/filetests/isa/x64/immediates.clif
View File

@@ -19,15 +19,15 @@ block0(v0: i64, v1: i64):
; movq %rsp, %rbp
; block0:
; movq %rdi, %r10
; addq %r10, const(VCodeConstant(0)), %r10
; addq %r10, const(0), %r10
; movq %r10, 0(%rsi)
; movq %rdi, %r11
; subq %r11, const(VCodeConstant(0)), %r11
; subq %r11, const(0), %r11
; movq %r11, 0(%rsi)
; movq %rdi, %rax
; andq %rax, const(VCodeConstant(0)), %rax
; andq %rax, const(0), %rax
; movq %rax, 0(%rsi)
; orq %rdi, const(VCodeConstant(0)), %rdi
; orq %rdi, const(0), %rdi
; movq %rdi, 0(%rsi)
; movq %rbp, %rsp
; popq %rbp

2
cranelift/filetests/filetests/isa/x64/narrowing.clif
View File

@@ -42,7 +42,7 @@ block0(v0: f64x2):
; block0:
; movdqa %xmm0, %xmm5
; cmppd $0, %xmm5, %xmm0, %xmm5
; load_const VCodeConstant(0), %xmm6
; movupd const(0), %xmm6
; andps %xmm5, %xmm6, %xmm5
; minpd %xmm0, %xmm5, %xmm0
; cvttpd2dq %xmm0, %xmm0

8
cranelift/filetests/filetests/isa/x64/shuffle-avx512.clif
View File

@@ -13,7 +13,7 @@ block0(v0: i8x16, v1: i8x16):
; movq %rsp, %rbp
; block0:
; movdqa %xmm0, %xmm6
; load_const VCodeConstant(0), %xmm0
; movdqu const(0), %xmm0
; movdqa %xmm6, %xmm8
; vpermi2b %xmm1, %xmm8, %xmm0, %xmm0
; movq %rbp, %rsp
@@ -33,8 +33,8 @@ block0(v0: i8x16, v1: i8x16):
; movq %rsp, %rbp
; block0:
; movdqa %xmm0, %xmm9
; load_const VCodeConstant(1), %xmm0
; load_const VCodeConstant(0), %xmm8
; movdqu const(1), %xmm0
; movdqu const(0), %xmm8
; movdqa %xmm9, %xmm11
; vpermi2b %xmm1, %xmm11, %xmm8, %xmm8
; andps %xmm0, %xmm8, %xmm0
@@ -52,7 +52,7 @@ block0(v0: i8x16, v1: i8x16):
; movq %rsp, %rbp
; block0:
; movdqa %xmm0, %xmm6
; load_const VCodeConstant(0), %xmm0
; movdqu const(0), %xmm0
; movdqa %xmm6, %xmm8
; vpermi2b %xmm1, %xmm8, %xmm0, %xmm0
; movq %rbp, %rsp

16
cranelift/filetests/filetests/isa/x64/simd-bitwise-compile.clif
View File

@@ -140,9 +140,9 @@ block0:
; pushq %rbp
; movq %rsp, %rbp
; block0:
; load_const VCodeConstant(0), %xmm0
; load_const VCodeConstant(0), %xmm2
; load_const VCodeConstant(0), %xmm6
; movdqu const(0), %xmm0
; movdqu const(0), %xmm2
; movdqu const(0), %xmm6
; pand %xmm2, %xmm0, %xmm2
; pandn %xmm0, %xmm6, %xmm0
; por %xmm0, %xmm2, %xmm0
@@ -205,11 +205,11 @@ block0(v0: i32):
; pushq %rbp
; movq %rsp, %rbp
; block0:
; load_const VCodeConstant(1), %xmm0
; movdqu const(1), %xmm0
; andq %rdi, $7, %rdi
; movd %edi, %xmm6
; psllw %xmm0, %xmm6, %xmm0
; lea const(VCodeConstant(0)), %rax
; lea const(0), %rax
; shlq $4, %rdi, %rdi
; movdqu 0(%rax,%rdi,1), %xmm14
; pand %xmm0, %xmm14, %xmm0
@@ -228,12 +228,12 @@ block0:
; pushq %rbp
; movq %rsp, %rbp
; block0:
; load_const VCodeConstant(1), %xmm0
; movdqu const(1), %xmm0
; movl $1, %r10d
; andq %r10, $7, %r10
; movd %r10d, %xmm6
; psrlw %xmm0, %xmm6, %xmm0
; lea const(VCodeConstant(0)), %rdi
; lea const(0), %rdi
; shlq $4, %r10, %r10
; movdqu 0(%rdi,%r10,1), %xmm14
; pand %xmm0, %xmm14, %xmm0
@@ -251,7 +251,7 @@ block0(v0: i32):
; pushq %rbp
; movq %rsp, %rbp
; block0:
; load_const VCodeConstant(0), %xmm9
; movdqu const(0), %xmm9
; andq %rdi, $7, %rdi
; movdqa %xmm9, %xmm0
; punpcklbw %xmm0, %xmm9, %xmm0

18
cranelift/filetests/filetests/isa/x64/simd-lane-access-compile.clif
View File

@@ -15,11 +15,11 @@ block0:
; pushq %rbp
; movq %rsp, %rbp
; block0:
; load_const VCodeConstant(3), %xmm0
; load_const VCodeConstant(2), %xmm5
; load_const VCodeConstant(0), %xmm3
; movdqu const(3), %xmm0
; movdqu const(2), %xmm5
; movdqu const(0), %xmm3
; pshufb %xmm0, %xmm3, %xmm0
; load_const VCodeConstant(1), %xmm7
; movdqu const(1), %xmm7
; pshufb %xmm5, %xmm7, %xmm5
; por %xmm0, %xmm5, %xmm0
; movq %rbp, %rsp
@@ -36,8 +36,8 @@ block0:
; pushq %rbp
; movq %rsp, %rbp
; block0:
; load_const VCodeConstant(1), %xmm0
; load_const VCodeConstant(0), %xmm2
; movdqu const(1), %xmm0
; movdqu const(0), %xmm2
; pshufb %xmm0, %xmm2, %xmm0
; movq %rbp, %rsp
; popq %rbp
@@ -54,9 +54,9 @@ block0:
; pushq %rbp
; movq %rsp, %rbp
; block0:
; load_const VCodeConstant(1), %xmm0
; load_const VCodeConstant(1), %xmm3
; load_const VCodeConstant(0), %xmm4
; movdqu const(1), %xmm0
; movdqu const(1), %xmm3
; movdqu const(0), %xmm4
; paddusb %xmm3, %xmm4, %xmm3
; pshufb %xmm0, %xmm3, %xmm0
; movq %rbp, %rsp

12
cranelift/filetests/filetests/isa/x64/simd-pairwise-add.clif
View File

@@ -13,7 +13,7 @@ block0(v0: i8x16):
; movq %rsp, %rbp
; block0:
; movdqa %xmm0, %xmm5
; load_const VCodeConstant(0), %xmm0
; movdqu const(0), %xmm0
; movdqa %xmm5, %xmm6
; pmaddubsw %xmm0, %xmm6, %xmm0
; movq %rbp, %rsp
@@ -31,7 +31,7 @@ block0(v0: i16x8):
; pushq %rbp
; movq %rsp, %rbp
; block0:
; load_const VCodeConstant(0), %xmm3
; movdqu const(0), %xmm3
; pmaddwd %xmm0, %xmm3, %xmm0
; movq %rbp, %rsp
; popq %rbp
@@ -48,7 +48,7 @@ block0(v0: i8x16):
; pushq %rbp
; movq %rsp, %rbp
; block0:
; load_const VCodeConstant(0), %xmm3
; movdqu const(0), %xmm3
; pmaddubsw %xmm0, %xmm3, %xmm0
; movq %rbp, %rsp
; popq %rbp
@@ -65,11 +65,11 @@ block0(v0: i16x8):
; pushq %rbp
; movq %rsp, %rbp
; block0:
; load_const VCodeConstant(0), %xmm3
; movdqu const(0), %xmm3
; pxor %xmm0, %xmm3, %xmm0
; load_const VCodeConstant(1), %xmm7
; movdqu const(1), %xmm7
; pmaddwd %xmm0, %xmm7, %xmm0
; load_const VCodeConstant(2), %xmm11
; movdqu const(2), %xmm11
; paddd %xmm0, %xmm11, %xmm0
; movq %rbp, %rsp
; popq %rbp

3
cranelift/filetests/filetests/isa/x64/sqmul_round_sat.clif
View File

@@ -10,10 +10,11 @@ block0(v0: i16x8, v1: i16x8):
; pushq %rbp
; movq %rsp, %rbp
; block0:
; load_const VCodeConstant(0), %xmm7
; movdqu const(0), %xmm7
; pmulhrsw %xmm0, %xmm1, %xmm0
; pcmpeqw %xmm7, %xmm0, %xmm7
; pxor %xmm0, %xmm7, %xmm0
; movq %rbp, %rsp
; popq %rbp
; ret

4
cranelift/filetests/filetests/isa/x64/uunarrow.clif
View File

@@ -14,10 +14,10 @@ block0(v0: f64x2):
; block0:
; xorpd %xmm3, %xmm3, %xmm3
; maxpd %xmm0, %xmm3, %xmm0
; load_const VCodeConstant(0), %xmm7
; movupd const(0), %xmm7
; minpd %xmm0, %xmm7, %xmm0
; roundpd $3, %xmm0, %xmm0
; load_const VCodeConstant(1), %xmm13
; movupd const(1), %xmm13
; addpd %xmm0, %xmm13, %xmm0
; shufps $136, %xmm0, %xmm3, %xmm0
; movq %rbp, %rsp